EECS 150 - Components and Design Techniques for Digital Systems Lec 03 – Field Programmable Gate Arrays 9-4-07ReviewQuestion from ThursCombinational vs. Sequential Digital CircuitsSequential logicSynchronous sequential digital systemsRecall: What makes Digital Systems tick?D-type edge-triggered flip-flopSlide 9Parallel to Serial Converter ExampleSlide 11Transistor-level Logic Circuits - LatchPositive Edge-triggered Flip-flopSummary: Representation of digital designsOutlineFPGA OverviewWhy FPGAs?Slide 18Slide 19Programmable LogicCanonical FormsSum-of-Products Canonical FormsSum-of-Products Canonical Form (cont’d)Four Alternative Two-level Implementations of F = AB + CWaveforms for the Four AlternativesIncompletely Specified FunctionsNotation for Incompletely Specified FunctionsProgrammable Logic Arrays (PLAs)Enabling ConceptBefore ProgrammingAfter ProgrammingAnnouncementsSlide 38FPGA VariationsUser ProgrammabilityIdealized FPGA Logic BlockBoolean Functions: 1 variableInteractive Quiz: Boolean Functions of 2 variables?How could you build a generic boolean logic circuit?Recall: Multiplexer/DemultiplexerMultiplexers/Selectors – a logical functionMultiplexers/Selectors: to implement logicCascading MultiplexersMultiplexers as Lookup Tables (LUTs)Multiplexers as LUTs (cont’d)LUT as general logic gate4-LUT ImplementationFPGA Generic Design FlowExample Partition, Placement, and RouteXilinx Virtex-E FloorplanVirtex-E Configurable Logic Block (CLB)Details of Virtex-E SliceXilinx FPGAs (interconnect detail)Virtex-E Input/Output block (IOB) detailVirtex-E Family of PartsXilinx FPGAsSummaryEECS 150 - Components and Design Techniques for Digital Systems Lec 03 – Field Programmable Gate Arrays 9-4-07 David CullerElectrical Engineering and Computer SciencesUniversity of California, Berkeleyhttp://www.eecs.berkeley.edu/~cullerhttp://inst.eecs.berkeley.edu/~cs1509/4/2007EECS 150, Fa07, Lec 03-fpga2Review•Building blocks of computer systems–ICs (Chips), PCBs, Chassis, Cables & Connectors•CMOS Transistors–Voltage controlled switches–Complementary forms (nmos, pmos)•Logic gates from CMOS transistors–Logic gates implement particular boolean functions»N inputs, 1 output–Serial and parallel switches–Dual structure–P-type “pull up” transmit 1–N-type •Complex gates: mux•Synchronous Sequential Elements [ today ]–D FlipFlops9/4/2007EECS 150, Fa07, Lec 03-fpga3Question from ThursHow does nFET behave • when EN is Hi, S = D = lo?• when EN is Hi, S = D = Hi?How does nFET behave • when EN is Hi, S = D = Hi?• when EN is Hi, S = D = lo?Together they go Rail-to-Rail☺9/4/2007EECS 150, Fa07, Lec 03-fpga4inputs outputssystemCombinational vs. Sequential Digital Circuits•Simple model of a digital system is a unit with inputs and outputs:•Combinational means "memory-less"–Digital circuit is combinational if its output valuesonly depend on its inputs9/4/2007EECS 150, Fa07, Lec 03-fpga5Sequential logic•Sequential systems–Exhibit behaviors (output values) that depend on current as well as previous inputs•All real circuits are sequential–Outputs do not change instantaneously after an input change–Why not, and why is it then sequential?•Fundamental abstraction of digital design is to reason (mostly) about steady-state behaviors–Examine outputs only after sufficient time has elapsed for the system to make its required changes and settle down9/4/2007EECS 150, Fa07, Lec 03-fpga6Synchronous sequential digital systems•Combinational circuit outputs depend only on current inputs–After sufficient time has elapsed•Sequential circuits have memory–Even after waiting for transient activity to finish•Steady-state abstraction: most designers use it when constructing sequential circuits:–Memory of system is its state–Changes in system state only allowed at specific times controlled by an external periodic signal (the clock)–Clock period is elapsed time between state changessufficiently long so that system reaches steady-state before next state change at end of period9/4/2007EECS 150, Fa07, Lec 03-fpga7Recall: What makes Digital Systems tick?CombinationalLogictimeclk9/4/2007EECS 150, Fa07, Lec 03-fpga8D-type edge-triggered flip-flop•The edge of the clock is used to sample the "D" input & send it to "Q” (positive edge triggering). –At all other times the output Q is independent of the input D (just stores previously sampled value). –The input must be stable for a short time before the clock edge.9/4/2007EECS 150, Fa07, Lec 03-fpga9D-type edge-triggered flip-flop•The edge of the clock is used to sample the "D" input & send it to "Q” (positive edge triggering). –At all other times the output Q is independent of the input D (just stores previously sampled value). –The input must be stable for a short time before the clock edge. 01010109/4/2007EECS 150, Fa07, Lec 03-fpga10Parallel to Serial Converter Example•4-bit version:•Operation:–cycle 1: load x, output x0–cycle i: output xiif LD=1 load FF from xi else from previous stage.•Each stage:LD=1x3 x2 x1 x0LD=0?? x3 x2 x1?? ?? x3 x2?? ?? ?? x39/4/2007EECS 150, Fa07, Lec 03-fpga11Parallel to Serial Converter Example•timing:9/4/2007EECS 150, Fa07, Lec 03-fpga12Transistor-level Logic Circuits - Latch•Positive Level-sensitive latch•Transistor Level•Positive Edge-triggered flip-flop built from two level-sensitive latches:clk’clkclkclk’D FlipFlop9/4/2007EECS 150, Fa07, Lec 03-fpga13Positive Edge-triggered Flip-flop•Flip-flop built from two latches:•When clk low, left latch acts as feedthrough, and Q is stored value of right latch.•When clk high left latch stores values and right latch acts as feedthrough.DD QQclk9/4/2007EECS 150, Fa07, Lec 03-fpga14scope of CS 150Summary: Representation of digital designs•Physical devices (transistors, relays)•Switches•Truth tables•Boolean algebra•Gates•Waveforms•Finite state behavior•Register-transfer behavior•Concurrent abstract specificationsmore depth than 61Cfocus on building systems9/4/2007EECS 150, Fa07, Lec 03-fpga15Outline•Review•What are FPGAs?•Why use FPGAs (a short history lesson).•Canonical Forms => Programmable Logic•FPGA variations•Internal logic blocks.•Designing with FPGAs.•Specifics of Xilinx Virtex-E series.Today’s reading• Katz: 9.4 pp 428-447 (especially 9.4.4)• XILINX Virtex-E FPGA data sheet (first 10 pages)9/4/2007EECS 150, Fa07, Lec 03-fpga16FPGA Overview•Basic idea:
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