Architectural DescriptionVirtex-E ArrayInput/Output BlockInput PathOutput PathI/O BankingConfigurable Logic BlocksLook-Up TablesStorage ElementsAdditional LogicArithmetic LogicBUFTsBlock SelectRAMProgrammable Routing MatrixLocal RoutingGeneral Purpose RoutingI/O RoutingDedicated RoutingClock RoutingGlobal Clock DistributionDigital Delay-Locked LoopsBoundary ScanInstruction SetData RegistersBit SequenceIdentification RegistersIncluding Boundary Scan in a DesignDevelopment SystemDesign ImplementationDesign VerificationConfigurationConfiguration ModesSlave-Serial ModeMaster-Serial ModeSelectMAP ModeWriteAbortBoundary-Scan ModeConfiguration SequenceDelaying ConfigurationStart-Up SequenceReadbackDesign ConsiderationsUsing DLLsIntroductionLibrary DLL SymbolsBUFGDLL Pin DescriptionsSource Clock Input — IClock Output — OCLKDLL Primitive Pin DescriptionsSource Clock Input — CLKINFeedback Clock Input — CLKFBReset Input — RST2x Clock Output — CLK2XClock Divide Output — CLKDV1x Clock Outputs — CLK[0|90|180|270]Locked Output — LOCKEDDLL PropertiesDuty Cycle Correction PropertyClock Divide PropertyStartup Delay PropertyVirtex-E DLL Location ConstraintsDesign FactorsInput ClockInput Clock ChangesOutput ClocksUseful Application ExamplesStandard UsageBoard Level De-skew of Multiple Non-Virtex-E DevicesDe-Skew of Clock and Its 2x MultipleVirtex-E 4x ClockUsing Block SelectRAM+ FeaturesOperating ModesRead Through (one clock edge)Write Back (one clock edge)Block SelectRAM+ CharacteristicsLibrary PrimitivesPort SignalsClock—CLK[A|B]Enable—EN[A|B]Write Enable—WE[A|B]Reset—RST[A|B]Address Bus—ADDR[A|B]<#:0>Data In Bus—DI[A|B]<#:0>Data Output Bus—DO[A|B]<#:0>Inverting Control PinsAddress MappingCreating Larger RAM StructuresLocation ConstraintsConflict ResolutionSingle Port TimingDual Port TimingInitializationInitialization in VHDL and SynopsysInitialization in Verilog and SynopsysDesign ExamplesCreating a 32-bit Single-Port RAMCreating Two Single-Port RAMsBlock Memory GenerationVHDL Initialization ExampleVerilog Initialization ExampleUsing SelectI/OIntroductionFundamentalsOverview of Supported I/O StandardsLVTTL — Low-Voltage TTLLVCMOS2 — Low-Voltage CMOS for 2.5 VoltsLVCMOS18 — 1.8 V Low Voltage CMOSPCI — Peripheral Component InterfaceGTL — Gunning Transceiver Logic TerminatedGTL+ — Gunning Transceiver Logic PlusHSTL — High-Speed Transceiver LogicSSTL3 — Stub Series Terminated Logic for 3.3VSSTL2 — Stub Series Terminated Logic for 2.5VCTT — Center Tap TerminatedAGP-2X — Advanced Graphics PortLVDS — Low Voltage Differential SignalBLVDS — Bus LVDSLVPECL — Low Voltage Positive Emitter Coupled LogicLibrary SymbolsIBUFIBUFGOBUFOBUFTIOBUFSelectI/O PropertiesInput Delay PropertiesIOB Flip-Flop/Latch PropertyLocation ConstraintsOutput Slew Rate PropertyOutput Drive Strength PropertyDesign ConsiderationsReference Voltage (VREF) PinsOutput Drive Source Voltage (VCCO) PinsTransmission Line EffectsTermination TechniquesSimultaneous Switching GuidelinesApplication ExamplesTermination ExamplesGTLGTL+HSTLSSTL3_ISSTL3_IISSTL2_ISSTL2_IICTTPCI33_3 & PCI66_3LVTTLLVCMOS2LVCMOS18AGP-2XLVDSLVPECLTermination Resistor PacksLVDS Design GuideCreating LVDS Global Clock Input BuffersHDL InstantiationVHDL InstantiationVerilog InstantiationLocation constraintsOptional N-sideVHDL InstantiationVerilog InstantiationLocation ConstraintsCreating LVDS Input BuffersHDL InstantiationVHDL InstantiationVerilog InstantiationLocation ConstraintsOptional N-sideVHDL InstantiationVerilog InstantiationLocation ConstraintsAdding an Input RegisterCreating LVDS Output BuffersHDL InstantiationVHDL InstantiationVerilog InstantiationLocation ConstraintsSynchronous vs. Asynchronous OutputsAdding an Output RegisterCreating LVDS Output 3-State BuffersHDL InstantiationVHDL InstantiationVerilog InstantiationLocation ConstraintsSynchronous vs. Asynchronous 3-State OutputsAdding Output and 3-State RegistersCreating a LVDS Bidirectional BufferHDL InstantiationVHDL InstantiationVerilog InstantiationLocation ConstraintsSynchronous vs. Asynchronous Bidirectional BuffersAdding Output and 3-State RegistersRevision HistoryVirtex-E Data Sheet© 2000-2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.DS022-2 (v2.4) July 17, 2002 www.xilinx.com Module 2 of 4Production Product Specification 1-800-255-7778 1Architectural DescriptionVirtex-E ArrayThe Virtex-E user-programmable gate array, shown inFigure 1, comprises two major configurable elements: con-figurable logic blocks (CLBs) and input/output blocks (IOBs).• CLBs provide the functional elements for constructing logic• IOBs provide the interface between the package pins and the CLBsCLBs interconnect through a general routing matrix (GRM).The GRM comprises an array of routing switches located atthe intersections of horizontal and vertical routing channels.Each CLB nests into a VersaBlock™ that also provides localrouting resources to connect the CLB to the GRM.The VersaRing™ I/O interface provides additional routingresources around the periphery of the device. This routingimproves I/O routability and facilitates pin locking.The Virtex-E architecture also includes the following circuitsthat connect to the GRM.• Dedicated block memories of 4096 bits each• Clock DLLs for clock-distribution delay compensation and clock domain control• 3-State buffers (BUFTs) associated with each CLB that drive dedicated segmentable horizontal routing resourcesValues stored in static memory cells control the configurablelogic elements and interconnect resources. These valuesload into the memory cells on power-up, and can reload ifnecessary to change the function of the device.Input/Output BlockThe Virtex-E IOB, Figure 2, features SelectI/O+ inputs andoutputs that support a wide variety of I/O signalling stan-dards, see Table 1. The three IOB storage elements function either asedge-triggered D-type flip-flops or as level-sensitive latches.Each IOB has a clock signal (CLK) shared by the threeflip-flops and independent clock enable signals for eachflip-flop. 0Virtex™-E 1.8 V Field Programmable Gate ArraysDS022-2 (v2.4) July 17, 200200Production Product SpecificationRFigure 1: Virtex-E Architecture
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