Spring 2007 Lec #8 -- HW Synthesis 1Verilog Synthesis• Synthesis vs. Compilation• Descriptions mapped to hardware• Verilog design patterns for best synthesisSpring 2007 Lec #8 -- HW Synthesis 2Logic Synthesis• Verilog and VHDL started out as simulation languages, but soonprograms were written to automatically convert Verilog code intolow-level circuit descriptions (netlists).•Synthesis converts Verilog (or other HDL) descriptions to animplementation using technology-specific primitives:– For FPGAs: LUTs, flip-flops, and RAM blocks– For ASICs: standard cell gate and flip-flop libraries, and memoryblocksSynthesisToolVerilogHDLcircuitnetlistSpring 2007 Lec #8 -- HW Synthesis 3Why Perform Logic Synthesis?1. Automatically manages many details of the design process:• Fewer bugs• Improves productivity2. Abstracts the design data (HDL description) from any particularimplementation technology• Designs can be re-synthesized targeting different chip technologies;E.g.: first implement in FPGA then later in ASIC3. In some cases, leads to a more optimal design than could beachieved by manual means (e.g.: logic optimization)Why Not Logic Synthesis?1. May lead to less than optimal designs in some casesSpring 2007 Lec #8 -- HW Synthesis 4How Does It Work?• Variety of general and ad-hoc (special case) methods:– Instantiation: maintains a library of primitive modules (AND, OR, etc.)and user defined modules– “Macro expansion”/substitution: a large set of language operators(+, -, Boolean operators, etc.) and constructs (if-else, case) expand intospecial circuits– Inference: special patterns are detected in the language descriptionand treated specially (e.g.,: inferring memory blocks from variabledeclaration and read/write statements, FSM detection and generationfrom “always @ (posedge clk)” blocks)– Logic optimization: Boolean operations are grouped and optimized withlogic minimization techniques– Structural reorganization: advanced techniques including sharing ofoperators, and retiming of circuits (moving FFs), and othersSpring 2007 Lec #8 -- HW Synthesis 5Operators• Logical operators map into primitivelogic gates• Arithmetic operators map into adders,subtractors, …– Unsigned 2s complement– Model carry: target is one-bit widerthat source– Watch out for *, %, and /• Relational operators generatecomparators• Shifts by constant amount are justwire connections– No logic involved• Variable shift amounts a wholedifferent story --- shifter• Conditional expression generates logicor MUXY = ~X << 2X[3]Y[0]Y[1]Y[2]X[0]X[1]X[2]Y[3]Y[4]Y[5]Spring 2007 Lec #8 -- HW Synthesis 6Synthesis vs. Compilation1561CLevels of RepresentationHigh Level Language Program (e.g., C)Assembly Language Program (e.g.,MIPS)Machine Language Program (MIPS)Control Signal SpecificationCompilerAssemblerMachine Interpretationtemp = v[k];v[k] = v[k+1];v[k+1] = temp;lw $to, 0($2)lw $t1, 4($2)sw$t1, 0($2)sw$t0, 4($2)0000 1001 1100 0110 1010 1111 0101 10001010 1111 0101 1000 0000 1001 1100 0110 1100 0110 1010 1111 0101 1000 0000 1001 0101 1000 0000 1001 1100 0110 1010 1111°°• Compiler– Recognizes all possibleconstructs in a formallydefined program language– Translates them to a machinelanguage representation ofexecution process• Synthesis– Recognizes a targetdependent subset of ahardware description language– Maps to collection ofconcrete hardware resources– Iterative tool in the designflowSpring 2007 Lec #8 -- HW Synthesis 7Simple Examplemodule foo (a,b,s0,s1,f);input [3:0] a;input [3:0] b;input s0,s1;output [3:0] f;reg f;always @ (a or b or s0 or s1)if (!s0 && s1 || s0) f=a; else f=b;endmodule• Should expand if-else into 4-bit wide multiplexer (a, b, f are 4-bit vectors) andoptimize/minimize the control logic:Spring 2007 Lec #8 -- HW Synthesis 8Module Templatemodule <top_module_name>(<port list>);/* Port declarations. followed by wire, reg, integer, task and function declarations *//* Describe hardware with one or more continuous assignments, always blocks, moduleinstantiations and gate instantiations */// Continuous assignmentwire <result_signal_name>;assign <result_signal_name> = <expression>;// always blockalways @(<event expression>)begin// Procedural assignments// if statements// case, casex, and casez statements// while, repeat and for loops// user task and user function callsend// Module instantiation<module_name> <instance_name> (<port list>);// Instantiation of built-in gate primitivegate_type_keyword (<port list>);endmodule• Order of these statements isirrelevant, all execute concurrently• Statements between the begin andend in an always block executesequentially from top to bottom(however, beware of blocking versusnon-blocking assignment)• Statements within a fork-joinstatement in an always blockexecute concurrentlySynthesis tools expects to find modules in this format.Spring 2007 Lec #8 -- HW Synthesis 9Procedural Assignments• Verilog has two types of assignments within always blocks:• Blocking procedural assignment “=“– RHS is executed and assignment is completed before the next statement isexecuted; e.g.,Assume A holds the value 1 … A=2; B=A; A is left with 2, B with 2.• Non-blocking procedural assignment “<=“– RHS is executed and assignment takes place at the end of the current time step(not clock cycle); e.g.,Assume A holds the value 1 … A<=2; B<=A; A is left with 2, B with 1.• Notion of “current time step” is tricky in synthesis, so to guarantee thatyour simulation matches the behavior of the synthesized circuit, followthese rules:i. Use blocking assignments to model combinational logic within an always blockii. Use non-blocking assignments to implement sequential logiciii. Do not mix blocking and non-blocking assignments in the same always blockiv. Do not make assignments to the same variable from more than one always blockSpring 2007 Lec #8 -- HW Synthesis 10Supported Verilog Constructs– Net types: wire, tri, supply1, supply0;register types: reg, integer, time (64bit reg); arrays of reg– Continuous assignments– Gate primitive and moduleinstantiations– always blocks, user tasks, userfunctions– inputs, outputs, and inouts to a module– All operators (+, -, *, /, %, <, >, <=, >=,==, !=, ===, !==, &&, ||, !, ~, &, ~&, |, ~|,^~, ~^, ^, <<, >>, ?:, { }, {{ }}) [Note: /and % are supported for compile-timeconstants and constant powers of 2]– Procedural statements: if-else-if,case, casex, casez,
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