Fall 2002 EECS150 - Lec02-CMOSPage 1EECS150 - Digital DesignLecture 2 - CMOSAugust 29, 2002John WawrzynekFall 2002 EECS150 - Lec02-CMOSPage 2Outline• Overview of Physical Implementations• CMOS devices• Announcements/Break• CMOS transistor circuits– basic logic gates– tri-state buffers–flip-flops• flip-flop timing basics• circuits• example useFall 2002 EECS150 - Lec02-CMOSPage 3Overview of Physical Implementations• Integrated Circuits (ICs)– CL, memory elements, analog interfaces. • Printed Circuits (PC) boards– substrate for ICs and interconnection, distribution of CLK, Vdd, and GND signals, heat dissipation. • Power Supplies– Converts line AC voltage to regulated DC low voltage levels. • Chassis (rack, card case, ...) – holds boards, power supply, provides physical interface to user or other systems. • Connectors and Cables. The stuff out of which we make systems.Fall 2002 EECS150 - Lec02-CMOSPage 4Integrated Circuits• Primarily Crystalline Silicon• 1mm - 25mm on a side• 100 - 200M transistors• (25 - 50M "gates")• 3 - 10 conductive layers• 2002 - feature size ~ 0.13um = 0.13 x 10-6m • “CMOS” most common -complementary metal oxide semiconductor• Package provides:– spreading of chip-level signal paths to board-level – heat dissipation. • Ceramic or plastic with gold wires. Chip in PackageFall 2002 EECS150 - Lec02-CMOSPage 5Printed Circuit Boards• fiberglass or ceramic• 1-20 conductive layers • 1-20in on a side • IC packages are soldered down.Multichip Modules (MCMs)• Multiple chips cirectly connected to a substrate. (silicon, ceramic, plastic, fiberglass) without chip packages.Fall 2002 EECS150 - Lec02-CMOSPage 6Integrated Circuits• Moore’s Law has fueled innovation for the last 3 decades.• “Number of transistors on a die doubles every 18 months.”• What are the side effects of Moore’s law?Fall 2002 EECS150 - Lec02-CMOSPage 7Integrated Circuits• Uses for digital IC technology today:– standard microprocessors• used in desktop PCs, and embedded applications• simple system design (mostly software development)– memory chips (DRAM, SRAM)– application specific ICs (ASICs)• custom designed to match particular application• can be optimized for low-power, low-cost, high-performance• high-design cost– field programmable logic devices (FPGAs, CPLDs)• customized to particular application• short time to market• relatively high part cost– standardized low-density components• still manufactured for compatibility with older system designsFall 2002 EECS150 - Lec02-CMOSPage 8CMOS DevicesCross SectionThe gate acts like a capacitor. A high voltage on the gate attracts charge into the channel. If a voltage exists between the source and drain a current will flow. In its simplest approximation the device acts like a switch.Top View• MOSFET (Metal Oxide Semiconductor Field Effect Transistor). nFETpFETFall 2002 EECS150 - Lec02-CMOSPage 9AnnouncementsIf you are on the wait list and would like to get into the class you must:1. Turn in an appeal for on third floor Soda2. Attend lectures and do the homework, the first two weeks. 3. In the second week of classes, go to the lab section in which you wish to enroll. Give the TA your name and student ID. 4. Later, we will process the waitlist based on these requests, and lab section openings. • Please note: Monday evening lab section will not be held (labor day). It will be held Thursday (5-8pm) evening instead.Fall 2002 EECS150 - Lec02-CMOSPage 10AnnouncementsReading assignment for this week.All of chapter 1Chapter 10 sections 1,2,7,8,9Homework exercise is posted.Questions about class policy etc. covered on Tuesday?Fall 2002 EECS150 - Lec02-CMOSPage 11Transistor-level Logic Circuits• Inverter (NOT gate):• NAND gate• Note: – out = 0 iff both a AND b = 1 therefore out = (ab)’– pFET network and nFET network are duals of one another.How about AND gate?Fall 2002 EECS150 - Lec02-CMOSPage 12Transistor-level Logic Circuits• nFET is used only to pass logic zero:• pFet is used only to pass logic one:Simple rule for wiring up MOSFETs: Note: This rule is sometimes violated by expert designers under special conditions.Fall 2002 EECS150 - Lec02-CMOSPage 13Transistor-level Logic Circuits• NAND gate• NOR gate• Note: – out = 0 iff both a AND b = 1 therefore out = (ab)’– Again pFET network and nFETnetwork are duals of one another.– Other more complex functions are possible. Ex: out = (a+bc)’Fall 2002 EECS150 - Lec02-CMOSPage 14Transistor-level Logic Circuits• Transistor circuit“high impedance” (output disconnected)• Variations• Tri-state BufferFall 2002 EECS150 - Lec02-CMOSPage 15Transistor-level Logic Circuits• MultiplexorIf s=1 then c=a else c=b• Transistor CircuitFall 2002 EECS150 - Lec02-CMOSPage 16D-type edge-triggered flip-flop• The edge of the clock is used to sample the "D" input & send it to "Q” (positive edge triggering). – At all other times the output Q is independent of the input D (just stores previously sampled value). – The input must be stable for a short time before the clock edge.Fall 2002 EECS150 - Lec02-CMOSPage 17Parallel to Serial Converter Example• 4-bit version:• Operation:– cycle 1: load x, output x0– cycle i: output xiif LD=1 load FF from xielse from previous stage.• Each stage:Fall 2002 EECS150 - Lec02-CMOSPage 18Parallel to Serial Converter Example• timing:Fall 2002 EECS150 - Lec02-CMOSPage 19Transistor-level Logic Circuits• Level-sensitive latch• Edge-triggered
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