Fall 2002 EECS150 - Lec18-countersPage 1EECS150 - Digital DesignLecture 18 - CountersOctober 24, 2002John WawrzynekFall 2002 EECS150 - Lec18-countersPage 2Counters• Special sequential circuits (FSMs) that sequence though a set outputs. • Examples:– binary counter: 000, 001, 010, 011, 100, 101, 110, 111, 000, 001, …– gray code counter: 000, 010, 110, 100, 101, 111, 011, 001, 000, 010, 110, …– one-hot counter: 0001, 0010, 0100, 1000, 0001, 0010, …– BCD counter: 0000, 0001, 0010, …, 1001, 0000, 0001– pseudo-random sequence generators: 10, 01, 00, 11, 10, 01, 00, ...• Moore machines with “ring” structure to STD: S3S0S2S1Fall 2002 EECS150 - Lec18-countersPage 3What are they used?• Examples from this semester:– Clock divider circuits– Network packet parser/filter control.– Bit-serial multiplier control circuitry (from HW)– In general: counters simplify controller design by • providing a specific number of cycles of action,• sometimes used in with a decoder to generate a sequence of control signals.÷6416MHzFall 2002 EECS150 - Lec18-countersPage 4Controller using Counters• Bit-serial multiplier:• Control Algorithm:FAA registerB registerHI register LOW registershiftBshiftAshiftHI shiftLOWcarrysumresetD-FF01selectSumrepeat n cycles { // outer (i) looprepeat n cycles{ // inner (j) loopshiftA, selectSum, shiftHI}shiftB, shiftHI, shiftLOW, reset}Note: The occurrence of a controlsignal x means x=1. The absenceof x means x=0.Fall 2002 EECS150 - Lec18-countersPage 5Controller using Counters• State Transition Diagram:– Assume presence of two counters. An “i” counter for the outer loop and “j” counter for inner loop.counterCLK RSTCE TCIDLECEi,CEjRSTiCEi,CEjINNER<inner contol>CEi,CEjRSTjOUTER<outer contol>STARTSTARTTCiTCjTCiTCjTC is asserted when the counter reaches it maximum count value.CE is “clock enable”. The counterincrements its value on the rising edge of the clock if CE is asserted.Fall 2002 EECS150 - Lec18-countersPage 6Controller using Counters• Controller circuit implementation:• Outputs:CEi= q2CEj= q1RSTi= q0RSTj= q2shiftA = q1shiftB = q2shiftLOW = q2shiftHI = q1+ q2reset = q2selectSUM = q1IDLES RINNERS ROUTERS RSTARTTCiTCjcresetq0q1q2Fall 2002 EECS150 - Lec18-countersPage 7How do we design counters?• For binary counters (most common case) incrementer circuit would work:• In Verilog, a counter is specified as: x = x+1;– This does not imply an adder– An incrementer is simpler than an adder– And a counter is simpler yet.• In general, the best way to understand counter design is to think of them as FSMs, and follow general procedure. But before that ...register+1Fall 2002 EECS150 - Lec18-countersPage 8“Ripple” countersA3A2A1A00000000100100011010001010110011110001001101010111100110111101111time• Each stage is ÷2 of previous.• Look at output waveforms:• Often called “asynchronous” counters.• A “T” flip-flop is a “toggle” flip-flop. Flips it state on cycles when T=1.CLKA0A1A2A3Fall 2002 EECS150 - Lec18-countersPage 9Synchronous Counters• Binary Counter Design:Start with 3-bit version and generalize:ab ca+b+c+c b a c+ b+ a+0 0 0 0 0 10 0 1 0 1 00 1 0 0 1 10 1 1 1 0 01 0 0 1 0 11 0 1 1 1 01 1 0 1 1 11 1 1 0 0 0a+ = a’b+= a ⊕ bcba 00 01 11 100 0 0 1 11 0 1 0 1c+= a’c + abc’ + b’c= c(a’+b’) + c’(ab)= c(ab)’ + c’(ab)= c ⊕ abAll outputs change with clock edge.Fall 2002 EECS150 - Lec18-countersPage 10Synchronous Counters• How do we extend to n-bits?• Extrapolate c+: d+= d ⊕ abc, e+= e ⊕ abcd• Has difficulty scaling (AND gate inputs grow with n)• CE is “count enable”, allows external control of counting, • TC is “terminal count”, is asserted on highest value, allows cascading, external sensing of occurrence of max value.ab ca+b+c+dd+bb+cc+aa+dd+CETCFall 2002 EECS150 - Lec18-countersPage 11Synchronous Countersbb+cc+aa+dd+CETC• How does this one scale?/ Delay grows α n• Generation of TC signals very similar to generation of carry signals in adder. • “Parallel Prefix” circuit reduces delay: a b c d e f g hTCa TCb TCc TCc TCd TCe TCf TCglog2nlog2nFall 2002 EECS150 - Lec18-countersPage 12Up-Down Counterc b a c+ b+ a+0 0 0 1 1 10 0 1 0 0 00 1 0 0 0 10 1 1 0 1 01 0 0 0 1 11 0 1 1 0 01 1 0 1 0 11 1 1 1 1 0Down-countFall 2002 EECS150 - Lec18-countersPage 13Odd Counts• Extra combinational logic can be added to terminate count before max value is reached:•Example: count to 12• Alternative:4-bit binarycounter= 11 ?reset= 11 ?4-bit binarycounterload4TCFall 2002 EECS150 - Lec18-countersPage 14Ring Counters• “one-hot” counters0001, 0010, 0100, 1000, 0001, …“Self-starting” version:• What are these good for?DQDQDQDQq3q2q1q0DQDQDQDQq3q2q1S RS R S R S Rq0 0 0 0 0resetFall 2002 EECS150 - Lec18-countersPage 15Ring CountersFall 2002 EECS150 - Lec18-countersPage 16Johnson CounterFall 2002 EECS150 - Lec18-countersPage 17Register Summary• All registers (this semester) based on Flip-flops:• Load-enable is a popular option:DQDQDQDQq3q2q1S RS R S R S Rq0 0 0 0 0resetd3d2d1d0DQDQDQDQq3q2q1S RS RS RS Rq0 0000resetd301d201d101d001loadXilinx flip-flops employ a clock enable (CE) for same purpose.Fall 2002 EECS150 - Lec18-countersPage 18Shift-registers• Parallel load shift register:• “Parallel-to-serial converter”• Also, works as “Serial-to-parallel converter”, if q values are connected out.• Also get used as controllers (ala “ring counters”)Fall 2002 EECS150 - Lec18-countersPage 19Universal
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