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Berkeley COMPSCI 150 - Lecture 17 – Memory 1

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1Spring 2005 EECS150 - Lec17-mem1Page 1EECS150 - Digital DesignLecture 17 – Memory 1March 17, 2005John WawrzynekSpring 2005 EECS150 - Lec17-mem1Page 2Memory Basics• Uses:Whenever a large collection of state elements is required.– data & program storage – general purpose registers – buffering – table lookups – CL implementation • Types:– RAM - random access memory – ROM - read only memory – EPROM, FLASH - electrically programmable read only memory • Example RAM: Register file from microprocessorregid = register identifier (address of word in memory)sizeof(regid) = log2(# of reg) WE = write enableclk2Spring 2005 EECS150 - Lec17-mem1Page 3Definitions Memory Interfaces for Accessing Data• Asynchronous (unclocked): A change in the address results in data appearing • Synchronous (clocked): A change in address, followed by an edge on CLK results in data appearing or write operation occurring.A common arrangement is to have synchronous write operations andasynchronous read operations.• Volatile:Looses its state when the power goes off. • Nonvolatile:Retains it state when power goes off.Spring 2005 EECS150 - Lec17-mem1Page 4Register File Internals• For read operations, functionally the regfile is equivalent to a 2-D array of flip-flops with tristateoutputs on each:• Cell with added write logic:How do we go from "regid" to "SEL"?These circuits are just functional abstractions of the actual circuits used.3Spring 2005 EECS150 - Lec17-mem1Page 5Regid (address) Decoding• The function of the address decoder is to generate a one-hot code word from the address.• The output is use for row selection.• Many different circuits exist for this function. A simple one is shown to the right.Spring 2005 EECS150 - Lec17-mem1Page 6Standard Internal Memory Organization • Special circuit tricks are used for the cell array to improve storage density. (We will look at these later)• RAM/ROM naming convention: – examples: 32 X 8, "32 by 8" => 32 8-bit words – 1M X 1, "1 meg by 1" => 1M 1-bit words 2-D arrary of bit cells. Each cell stores one bit of data.4Spring 2005 EECS150 - Lec17-mem1Page 7Read Only Memory (ROM)• Simply for of memory. No write operation needed.• Functional Equivalence:• Full tri-state buffers are not needed at each cell point.• In practice, single transistors are used to implement zero cells. Logic one’s are derived through precharging or bit-line pullup transistor.Connections to Vddused to store a logic 1, connections to GND for storing logic 0.address decoderbit-cell arraySpring 2005 EECS150 - Lec17-mem1Page 8Column MUX in ROMs and RAMs: • Controls physical aspect ratio– Important for physical layout and to control delay on wires.• In DRAM, allows time-multiplexing of chip address pins5Spring 2005 EECS150 - Lec17-mem1Page 9Cascading Memory Modules (or chips) • Example: assemblage of 256 x 8 ROM using 256 x 4 modules:• example: 1K x * ROM using 256 x 4 modules:• each module has tri-state outputs: Spring 2005 EECS150 - Lec17-mem1Page 10Memory Components Types:• Volatile:– Random Access Memory (RAM): • DRAM "dynamic" • SRAM "static" • Non-volatile:– Read Only Memory (ROM): • Mask ROM "mask programmable" • EPROM "electrically programmable" • EEPROM "erasable electrically programmable" • FLASH memory - similar to EEPROM with programmer integrated on chip6Spring 2005 EECS150 - Lec17-mem1Page 11Volatile Memory Comparison • SRAM Cell• Larger cell  lower density, higher cost/bit • No refresh required • Simple read  faster access • Standard IC process  natural for integration with logic• DRAM Cell• Smaller cell  higher density, lower cost/bit • Needs periodic refresh, and refresh after read • Complex read  longer access time • Special IC process  difficult to integrate with logic circuitsword linebit linebit lineword linebit lineThe primary difference between different memory types is the bit cell.Spring 2005 EECS150 - Lec17-mem1Page 12Multi-ported Memory• Motivation:– Consider CPU core register file:• 1 read or write per cycle limits processor performance.• Complicates pipelining. Difficult for different instructions to simultaneously read or write regfile.• Common arrangement in pipelined CPUs is 2 read ports and 1 write port.databufferdisk/networkCPU• Motivation:– I/O data buffering:• dual-porting allows both sides to simultaneously access memory at full bandwidth. addradataaRWaaddrbdatabRWbDual-portMemoryselaselbselcdataadatabdatacRegfile7Spring 2005 EECS150 - Lec17-mem1Page 13Dual-ported Memory Internals• Add decoder, another set of read/write logic, bits lines, word lines:• Example cell: SRAM• Repeat everything but cross-coupled inverters.• This scheme extends up to a couple more ports, then need to add additional transistors.decadecbcellarrayr/w logicr/w logicdata portsaddressportsb2b2b1b1WL2WL1Spring 2005 EECS150 - Lec17-mem1Page 14Memory in Desktop Computer Systems: • SRAM(lower density, higher speed) used in CPU register file, on- and off-chip caches.• DRAM(higher density, lower speed) used in main memoryClosing the GAP: 1. Caches are growing in size.2. Innovation targeted towards higher bandwidth for memory systems:– SDRAM - synchronous DRAM – RDRAM - Rambus DRAM – EDORAM - extended data out SRAM – Three-dimensional RAM – hyper-page mode DRAM video RAM – multibank DRAM8Spring 2005 EECS150 - Lec17-mem1Page 15Important DRAM Examples:• EDO - extended data out (similar to fast-page mode) – RAS cycle fetched rows of data from cell array blocks (long access time, around 100ns)– Subsequent CAS cycles quickly access data from row buffers if within an address page (page is around 256 Bytes) • SDRAM - synchronous DRAM– clocked interface – uses dual banks internally. Start access in one bank then next, then receive data from first then second. • DDR - Double data rate SDRAM – Uses both rising (positive edge) and falling (negative) edge of clock for data transfer. (typical 100MHz clock with 200 MHz transfer). • RDRAM - Rambus DRAM – Entire data blocks are access and transferred out on a high-speed bus-like interface (500 MB/s, 1.6 GB/s) – Tricky system level design. More expensive memory chips. Spring 2005 EECS150 - Lec17-mem1Page 16Non-volatile Memory • Mask ROM – Used with logic circuits for tables etc.– Contents fixed at IC fab time (truly write once!) • EPROM (erasable


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