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Berkeley COMPSCI 150 - Homework

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CS150, Fall 2008 HW11 Due Friday, Dec 12, 2:10 PM The first three questions concern 8, 16, and 32 bit microcontroller chips that all have family members available for under $1. The files referenced are available at: http://www.eecs.berkeley.edu/~pister/150fa08 1) Look at the users guide for the Texas Instruments TI MSP430 a. Is this a Princeton or Harvard architecture? How many bits? (Fig 1-1) b. What is the maximum number of bytes available for program and data memory? (Fig 1-2) c. How many inputs and outputs are there from the register file? (Fig. 3-1) d. Give an example of an instruction that can execute in a single cycle. What is the most cycles that it takes for an instruction to execute, and how many bytes long is that instruction? (Table 3-16) (Extra for experts: what does that instruction do?) 2) Look at the paper on the ARM Cortex-M3 a. Is this a Princeton or a Harvard architecture? How many bits? b. Is the first paragraph in section 2.1 truth, or marketing hype? c. How does the M3 memory map differ from the MSP430? (Figure 4) d. What does the Bit Band Aliased region let you do? Is it wasteful of address space (i.e. it uses 32MB of address space – should I care?) 3) Look at the users guide for the Atmel ATmega128 a. Is this a Princeton or a Harvard architecture? How many bits? b. Are the program counter and stack pointer registers part of the main register file? (Fig 2) 4) For the simplified 32 bit processor that we’ve been working with in class (on the following pages) a. Use copies of the following page to trace the execution of i. back-to-back ADD3 instructions ii. PUSH R2 iii. A branch taken, and a branch not taken b. Which instructions require a field from the IR to pass through the ALU? Specify which bits, and if they need to be shifted, sign extended, etc. c. What instructions would you need to use to load -243 into R2? d. What changes do you need to make to the architecture to allow the process status word to be PUSHed and POPed? e. Assuming that the IR and the PSW are part of the control FSM (and hold most of its state) how many additional bits of state do you need in the control FSM? f. Draw a subset of the state transition (bubble) diagram which implements only ADD3, LD2, ST2, and BRxCLK INC_PC LD_IR MEM_ADDR (PC or ALU) ALU_OP REG_EN (and source: ALU or MD bus) MA bus MD bus Reg input bus PCAn instruction set vaguely inspired by ARM Thumb2: Op-code mnemonic args 0000 LD3 Rd, Rn, Rm Rd <- M(Rn+Rm) 0001 ST3 Rd, Rn, Rm M(Rn+Rm) <- Rd 0010 ADD3 Rd, Rn, Rm Rd <- Rn+Rm 0011 SUB3 Rd, Rn, Rm Rd <- Rn-Rm 0100 LSL Rd, Rn, shift logical left shift (zero pad) 0101 LSR Rd, Rn, shift logical right shift (zero pad) 0110 ASR Rd, Rn, shift arithmetic right shift (sign extend) 0111 ROT Rd, Rn, shift rotate 1000 LD2 Rd, Rn, #immed Rd <- M(Rn+immed*4); immed=0..15 1001 ST2 Rd, Rn, #immed M(Rn+immed*4) <- Rd 1010 ADD2 Rd, Rn, #immed Rd<- Rn + immed 1011 SUB2 Rd, Rn, #immed Rd<- Rn - immed 1100 LD1 Rd, #immed Rd <- immed; immed = 0..255 1101 BRx cond, offset if (cond) PC += offset*2 + 2; offset =-512..+511 1110 logic ops type, Rd, Rn Rd <- Rd op Rn 1111 various Branch condition: 00…11 = EQ, GE, LT, Carry Logic operations: 00… = AND, OR, XOR, NOT, … Various op-codes include PUSH Rd M(R14) <-Rd; R14-=4 POP Rd R14+=4; Rd<-M(R14) CALL Rd PUSH R15; R15 <- Rd RTS POP R15 RTI POP PSW; POP PCGood final exam questions (not due as homework): 1. What capabilities does the shifter need to implement? 2. What would this look like as a Harvard architecture? With what impact on performance? 3. How does the 16 bit IR get loaded from the 32 bit MD bus? 4. Design the interface between the IR and the ALU (including the MUX) 5. Design the register file down to transistors. 6. In an earlier day, the register file would have had a single output, which would have gone directly to one of the ALU inputs. The output of the ALU would have gone to one of three registers: an accumulator (ACC), a Memory Address Register (MAR), and a Memory Data Register (MDR). The ACC was the other input to the ALU, the MAR is the sole driver of the address input to the memory, and the MDR is the sole path into and out of the memory data port. How many cycles does it take with this architecture to execute an ADD3? Reg file 16x32 1W 3R (+PC) R14 = SP R15 = PC B A Shifter D Memory A IR


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Berkeley COMPSCI 150 - Homework

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