Fall 2011 EECS150 Lecture 16Page 1EECS150 - Digital DesignLecture 16 – CountersOctober 20, 2011Elad AlonElectrical Engineering and Computer SciencesUniversity of California, Berkeleyhttp://www-inst.eecs.berkeley.edu/~cs150Fall 2011 EECS150 Lecture 16Page 2Announcements• Midterm next Thurs. 6-8pm sharp,141 McCone• Elad will hold a review session next Mon. evening at 7pm in 540A/B Cory• No lecture next Thurs.Fall 2011 EECS150 Lecture 16Page 3Counters• Special sequential circuits (FSMs) that repeatedly sequence through a set of outputs. •Examples:– binary counter: 000, 001, 010, 011, 100, 101, 110, 111, 000, – gray code counter: 000, 010, 110, 100, 101, 111, 011, 001, 000, 010, 110, …– one-hot counter: 0001, 0010, 0100, 1000, 0001, 0010, …– BCD counter: 0000, 0001, 0010, …, 1001, 0000, 0001– pseudo-random sequence generators: 10, 01, 00, 11, 10, 01, 00, ...• Moore machines with “ring” structure in State Transition Diagram: S3S0S2S1Fall 2011 EECS150 Lecture 16Page 4What Are They Used For? (1)• Counters are commonly used in hardware designs because most (if not all) computations that we put into hardware include iteration (looping). Examples:– Shift-and-add multiplication scheme.– Bit serial communication circuits (must count one word’s worth of serial bits.)• Other uses for counter:– Clock divider circuits– Systematic inspection of data-structures• Example: Network packet parser/filter control.1/6416MHzFall 2011 EECS150 Lecture 16Page 5What Are They Used For? (2)• Counters simplify “controller” design by:– providing a specific number of cycles of action,– sometimes used with a decoder to generate a sequence of timed control signals.Fall 2011 EECS150 Lecture 16Page 6Example Circuit using Counters for Control• Bit-serial multiplier:Fall 2011 EECS150 Lecture 16Page 7Example Circuit using Counters for Control• Bit-serial multiplier (n2cycles, one bit of result finalized every n cycles):• Control Algorithm:repeat n cycles { // outer (i) looprepeat n cycles{ // inner (j) loopshiftA, selectSum, shiftHI}shiftB, shiftHI, shiftLOW, reset}Note: The occurrence of a controlsignal x means x=1. The absenceof x means x=0.Fall 2011 EECS150 Lecture 16Page 8Controller Using Counters• State Transition Diagram:– Assume presence of two binary counters. An “i” counter for the outer loop and “j” counter for inner loop.TC is asserted when the counter reaches it maximum count value.CE is “count enable”. The counterincrements its value on the rising edge of the clock if CE is asserted.Fall 2011 EECS150 Lecture 16Page 9Controller using Counters• Controller circuit implementation:• Outputs:CEi= q2CEj= q1RSTi= q0RSTj= q2shiftA = q1shiftB = q2shiftLOW = q2shiftHI = q1+ q2reset = q2selectSUM = q1Fall 2011 EECS150 Lecture 16Page 10How Do We Design Counters?• For binary counters (most common case) incrementer circuit would work:• In Verilog, a counter is specified as: x = x+1;–This does not imply a full-blown adder– An incrementer is simpler than an adder– And a counter can be simpler yet.• Can often use special optimizations for counters. But, if in doubt, think of a counter as an FSM and follow general procedure. register+1Fall 2011 EECS150 Lecture 16Page 11Synchronous Counters•Binary Counter Design:Start with 3-bit version and generalize:c b a c+ b+ a+0 0 0 0 0 10 0 1 0 1 00 1 0 0 1 10 1 1 1 0 01 0 0 1 0 11 0 1 1 1 01 1 0 1 1 11 1 1 0 0 0a+ = a’b+= a ⊕ bcba 00 01 11 100 0 0 1 11 0 1 0 1c+= a’c + abc’ + b’c= c(a’+b’) + c’(ab)= c(ab)’ + c’(ab)= c ⊕ abAll outputs change with clock edge.Fall 2011 EECS150 Lecture 16Page 12Synchronous Counter• Good news: can be reasonable fast– Critical path is n-bit AND + XOR• Bad news: hardware grows somewhat quickly with n– AND gate size grows with n• How do we extend to n bits?–Extrapolate:Fall 2011 EECS150 Lecture 16Page 13Alternative Counter Design• Good news: hardware simply linear with n• Bad news: delay also linear with n…Fall 2011 EECS150 Lecture 16Page 14Up-Down Counterc b a c+ b+ a+0 0 0 1 1 10 0 1 0 0 00 1 0 0 0 10 1 1 0 1 01 0 0 0 1 11 0 1 1 0 01 1 0 1 0 11 1 1 1 1 0Down-countQuickTime™ and aTIFF (Uncompressed) decompressorare needed to see this picture.Fall 2011 EECS150 Lecture 16Page 15Odd Counts• Extra combinational logic can be added to terminate count before max value is reached:•Example: count to 12• Alternative:Fall 2011 EECS150 Lecture 16Page 16Ring Counters• “one-hot” counters0001, 0010, 0100, 1000, 0001, …“Self-starting” version:• What are these good for?Fall 2011 EECS150 Lecture 16Page 17Johnson CounterFall 2011 EECS150 Lecture 16Page 18Asynchronous “Ripple” CountersA3A2A1A00000000100100011010001010110011110001001101010111100110111101111time• Each stage is 2 of previous.• Look at output waveforms:• Often called “asynchronous”counters.• A “T” flip-flop is a “toggle” flip-flop. Flips its state on cycles when T=1.CLKA0A1A2A3Forbidden in Synchronous
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