CS 150 - Spring 2007 – Lec. #11: Course Project - 1Videoconferencing Project! Project Concept and Background! Checkpoint Structure! Bells and WhistlesCS 150 - Spring 2007 – Lec. #11: Course Project - 2Objectives! Broad “brush” overview of the project! Details will be covered in the lab lectures, startingnext week! NOTE: anything discussed in the lab lectures andproject checkpoint write-ups supercedes what Idescribe here!" Neil and Allen have a working implementation of the project" They know the project better than I do! Listen to them!CS 150 - Spring 2007 – Lec. #11: Course Project - 3Course Project: VideoconferencingSystem! Not quite this… but:" Video camera capture" CRT video display" Serial compressed video2-way transmission betweentwo stations"Wireless communications" (no audio this semester)" Implemented in aXilinx FPGA on theCalinx boards in the lab" Groups of two -- your Lab #4/#5 partner" Commit to a TA now for grading purposesCS 150 - Spring 2007 – Lec. #11: Course Project - 4Calinx EECS 150 Lab/Project ProtoboardFlash Card &Micro-drive PortVideo Encoder &DecoderAC ’97 Codec &Power AmpVideo & Audio PortsFour 100 MbEthernet Ports8 Meg x 32SDRAMQuad EthernetTransceiverXilinxVirtex 2000ESeven SegmentLED DisplaysPrototypeAreaCS 150 - Spring 2007 – Lec. #11: Course Project - 5Complete Videoconferencing SystemDisplayVideo EncoderVideo Encoder(Checkpoint #1)Video DecoderCameraVideostreamVideoDecoderCheckpoint #2Checkpoint #4SDRAM(Checkpoint #0)Multiport SDRAMMemory SystemMultiportArbitrationWireless Transceiver(Checkpoint #3)CS 150 - Spring 2007 – Lec. #11: Course Project - 6Checkpoint #0/#1/#2:SDRAM Interface! Memory protocols" Bus arbitration" Address phase" Data phase! DRAM is large, but few address lines and slow" Row & col address" Wait states! Synchronous DRAM provides fast synchronous access currentblock" Little like a cache in the DRAM" Fast burst of data!Arbitration for shared resourceCS 150 - Spring 2007 – Lec. #11: Course Project - 7Checkpoint #1: Video Encoding! Pixel Array:" Digital image represented bymatrix of values, where each is afunction of the informationsurrounding it in the image; singleelement in image matrix: pictureelement or pixel (includes info forall color components)" Array size varies for differentapps and costs: some common sizesshown! Frames:" Illusion of motion created by successively flashing still pictures called framesHigh-Definition Television (HDTV), 2 MpxWorkstation, 1 MpxPC/Mac,1‡2 MpxVideo, 300 KpxSIF,82 KpxHigh-Definition Television (HDTV), 1 MpxCS 150 - Spring 2007 – Lec. #11: Course Project - 8Checkpoint #1: Video Encoding! Video details fairly complex and involve many choices:" NTSC vs. PAL, HDTV, …" Interleaved even-odd frames (TV) vs. progress scan (computer anddigital displays)" Frame size, frame rate" Pixel encodings: RGB, YUV/YCB (Luminance, Chrominance --brightness plus color difference signals)" Subsampling to reduce data demands (compression trick)" Inputs: ITU-R BT.601 Format (Digital Broadcast NTSC)" Outputs: Component video, S-video to drive LCDs in lab" Fortunately, Calinx board has a chip on-board that deals with muchof the grungy details …CS 150 - Spring 2007 – Lec. #11: Course Project - 9ITU-R BT.656 Details! Interfacing details for ITU-601Pixels per line 858Lines per frame 525Frames/sec 29.97Pixels/sec 13.5 MViewable pixels/line 720Viewable lines/frame 487! With 4:2:2 chroma sub-sampling,send 2 words/pixel (Cr/Y/Cb/Y)! Words/sec = 27MEncoder runs off a 27MHz clock! Control info (horizontal & verticalsynch) is multiplexed on data lines! Encoder data stream show to right! See video tutorial documents oncourse documentation web page!718 719 720 721 0 1 2359 360 0 1359 360 0 1736732( )368366()368366()857863)(Y 718Y 719C 360BY 720C 360RY 721C 359BC 359RY 736(732)C 368(366)BC 368(366)RY 855(861)C 428(431)BY 856(862)Y 857(863)C 0BY 0C 0RY 1C 428(431)RC 0BY 0Y 1C 0RC 359BY 718Y 719C 359RLast sampleof digital active lineSample datafor O instantFirst sampleof digital active lineHLuminancedata, YChrominancedata, CRChrominancedata, CBReplaced bytiming referencesignalReplaced bydigital blanking dataReplaced bytiming referencesignalEnd ofactive videoStart ofactive videoTiming reference signalsNote 1 – Sample identification numbers in parentheses are for 625-line systems where these differ from those for 525-line systems. (See also Recommendation ITU-R BT.803.)FIGURE 1Composition of interface data streamD01 CS 150 - Spring 2007 – Lec. #11: Course Project - 10Checkpoint #1: Video Encoder! Display driver processes pixels within frame buffer! Drive ADV7194 video encoder device to output correct NTSC video! Gain lots of experience reading data sheets! Dictates the 27 MHz operation rate" Used throughout graphics subsystemCS 150 - Spring 2007 – Lec. #11: Course Project - 11Calinx On-Board Video Encoder! Analog Devices ADV7194: ITU 601/656 in, Composite Video Out! Supports:" Multiple input formats and outputs" Operational modes, slave/master" Used in default mode: ITU-601 as slaves-video output! Digital input side connected to Virtex pins! Analog output side wired to on boardconnectors or headers! I2C interface for initialization:" Wired to VirtexCS 150 - Spring 2007 – Lec. #11: Course Project - 12SDRAM READ Burst TimingCS 150 - Spring 2007 – Lec. #11: Course Project - 13Checkpoint #2: Video Decode! Pretty much the reverse of the encodingprocess of Checkpoint #1! We will provide the base Verilog for video decode! You will need to integrate video decode with yourSDRAM arbitrated write port! Integrate with your Checkpoint #1CS 150 - Spring 2007 – Lec. #11: Course Project - 14Checkpoint #3: Wireless Transceiver! This will involve interfacing tothe wireless transceiver chip onthe Calinx2 board! Neil working on a cleardescription of how this worksCS 150 - Spring 2007 – Lec. #11: Course Project - 15Checkpoint Build Up to Complete Project! Week #7: Lab #6/Checkpoint #0 -- Basic SDRAM Subsystem! Week #8: Checkpoint #1 -- SDRAM to Video Display (Encoder)! Week #9: Checkpoint #2 -- Local Video System" Video Capture (Decoder) to SDRAM to Video Display (Encoder)" Video Decoder Verilog will be provided to you! Week #10/11 : Checkpoint #3 -- Wireless Transceiver" Midterm #2 scheduled for Week #10" Spring break between Week #10 and #11! Week #12/13: Checkpoint #4 -- Putting it altogether" Video Capture to SDRAM to Wireless Transceiver to SDRAM toVideo Display!
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