EECS 150 - Components and Design Techniques for Digital Systems Lec 04 – Hardware Description Languages / Verilog 9/6/2007ReviewOutlineRemember: to design is to representDesign FlowNetlistSlide 7Slide 8Slide 9Slide 10Design EntryHDLsDesign MethodologyQuick History of HDLsVerilogVerilog IntroductionStructural Model - XORStructural Model: 2-to1 muxSimple Behavioral Model2-to-1 mux behavioral descriptionBehavioral 4-to1 muxMixed Structural/Behavioral ModelAnnouncementsVerilog HelpVerilog Data Types and ValuesVerilog NumbersVerilog OperatorsVerilog VariablesVerilog ModuleVerilog Continuous AssignmentComparator ExampleSlide 32Simple Behavioral Model - the always blockalways BlockWhat Verilog generates storage elements?State ExampleState Example2 – Non blockingState Example2 – interactive quiz“Complete” AssignmentsIncomplete TriggersBehavioral with Bit VectorsVerilog ifSlide 44Verilog caseSlide 46Verilog case (cont)Parallel CaseVerilog casexcasex ExampleSequential LogicTestbenchFinal thoughts© UC BerkeleyEECS 150 - Components and Design Techniques for Digital Systems Lec 04 – Hardware Description Languages / Verilog9/6/2007 David CullerElectrical Engineering and Computer SciencesUniversity of California, Berkeleyhttp://www.eecs.berkeley.edu/~cullerhttp://inst.eecs.berkeley.edu/~cs1509/6/2007EECS 150, Fa07, Lec 04-HDL2© UC BerkeleyReview•Advancing technology changes the trade-offs and design techniques–2x transistors per chip every 18 months•ASIC, Programmable Logic, Microprocessor•Programmable logic invests chip real-estate to reduce design time & time to market–Canonical Forms, Logic Minimization, PLAs, •FPGA: –programmable interconnect, –configurable logic blocks»LUT + storage–Block RAM–IO Blocks9/6/2007EECS 150, Fa07, Lec 04-HDL3© UC BerkeleyOutline•Netlists•Design flow•What is a HDL?•Verilog•Announcements•Structural models•Behavioral models•Elements of the language•Lots of examples9/6/2007EECS 150, Fa07, Lec 04-HDL4© UC BerkeleyRemember: to design is to represent•How do we represent digital designs?•Components–Logic symbol, truth table–Storage symbol, timing diagram•Connections–SchematicsHuman readable or machine readable???9/6/2007EECS 150, Fa07, Lec 04-HDL5© UC BerkeleyDesign FlowDesignEntryHigh-level AnalysisTechnologyMappingLow-levelAnalysis9/6/2007EECS 150, Fa07, Lec 04-HDL6© UC BerkeleyNetlist•A key data structure (or representation) in the design process is the “netlist”:–Network List•A netlist lists components and connects them with nodes:ex:g1 "and" n1 n2 n5g2 "and" n3 n4 n6g3 "or" n5 n6 n7Alternative format:n1 g1.in1 n2 g1.in2n3 g2.in1n4 g2.in2n5 g1.out g3.in1n6 g2.out g3.in2n7 g3.outg1 "and"g2 "and"g3 "or"n 1n 2n 3n 4n 5n 6n 7•Netlist is needed for simulation and implementation.•Could be at the transistor level, gate level, ...•Could be hierarchical or flat.•How do we generate a netlist?g1g2g39/6/2007EECS 150, Fa07, Lec 04-HDL7© UC BerkeleyDesign Flow•Circuit is described and represented:–Graphically (Schematics)–Textually (HDL)•Result of circuit specification (and compilation) is a netlist of:–generic primitives - logic gates, flip-flops, or–technology specific primitives - LUTs/CLBs, transistors, discrete gates, or–higher level library elements - adders, ALUs, register files, decoders, etc.DesignEntryHigh-level AnalysisTechnologyMappingLow-levelAnalysis9/6/2007EECS 150, Fa07, Lec 04-HDL8© UC BerkeleyDesign Flow•High-level Analysis is used to verify:–correct function–rough:»timing»power»cost•Common tools used are:–simulator - check functional correctness, and–static timing analyzer»estimates circuit delays based on timing model and delay parameters for library elements (or primitives).DesignEntryHigh-level AnalysisTechnologyMappingLow-levelAnalysis9/6/2007EECS 150, Fa07, Lec 04-HDL9© UC BerkeleyDesign Flow•Technology Mapping:–Converts netlist to implementation technology dependent details»Expands library elements,»performs:•partitioning, •placement, •routing•Low-level Analysis–Simulation and Analysis Tools perform low-level checks with:»accurate timing models,»wire delay–For FPGAs this step could also use the actual device.DesignEntryHigh-level AnalysisTechnologyMappingLow-levelAnalysis9/6/2007EECS 150, Fa07, Lec 04-HDL10© UC BerkeleyDesign FlowNetlist:used between andinternally for all steps.DesignEntryHigh-level AnalysisTechnologyMappingLow-levelAnalysis9/6/2007EECS 150, Fa07, Lec 04-HDL11© UC BerkeleyDesign Entry•Schematic entry/editing used to be the standard method in industry•Used in EECS150 until recentlySchematics are intuitive. They match our use of gate-level or block diagrams.Somewhat physical. They imply a physical implementation.Require a special tool (editor).Unless hierarchy is carefully designed, schematics can be confusing and difficult to follow.•Hardware Description Languages (HDLs) are the new standard–except for PC board design, where schematics are still used.9/6/2007EECS 150, Fa07, Lec 04-HDL12© UC BerkeleyHDLs•Basic Idea:–Language constructs describe circuits with two basic forms:–Structural descriptions similar to hierarchical netlist.–Behavioral descriptions use higher-level constructs (similar to conventional programming).•Originally designed to help in abstraction and simulation.–Now “logic synthesis” tools exist to automatically convert from behavioral descriptions to gate netlist.–Greatly improves designer productivity.–However, this may lead you to falsely believe that hardware design can be reduced to writing programs!•“Structural” example:Decoder(output x0,x1,x2,x3;inputs a,b){wire abar, bbar;inv(bbar, b);inv(abar, a);nand(x0, abar, bbar);nand(x1, abar, b );nand(x2, a, bbar);nand(x3, a, b );} •“Behavioral” example:Decoder(output x0,x1,x2,x3;inputs a,b){case [a b]00: [x0 x1 x2 x3] = 0x0;01: [x0 x1 x2 x3] = 0x2;10: [x0 x1 x2 x3] = 0x4;11: [x0 x1 x2 x3] = 0x8; endcase;}9/6/2007EECS 150, Fa07, Lec 04-HDL13© UC BerkeleyDesign MethodologyHDLSpecificationStructure and Function(Behavior) of a DesignSimulationVerification: DesignBehave as Required?Functional: I/O BehaviorRegister-Level (Architectural)Logic-Level (Gates)Transistor-Level (Electrical)Timing: Waveform BehaviorSynthesisGeneration: MapSpecification toImplementation9/6/2007EECS 150, Fa07, Lec 04-HDL14© UC BerkeleyQuick History of HDLs•ISP (circa 1977) - research project at
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