Videoconferencing ProjectObjectivesCourse Project: Videoconferencing SystemCalinx EECS 150 Lab/Project ProtoboardComplete Videoconferencing SystemCheckpoint #0/#1/#2: SDRAM InterfaceCheckpoint #1: Video EncodingSlide 8ITU-R BT.656 DetailsCheckpoint #1: Video EncoderCalinx On-Board Video EncoderSDRAM READ Burst TimingCheckpoint #2: Video DecodeCheckpoint #3: Wireless TransceiverCheckpoint Build Up to Complete ProjectPossible Bells and WhistlesCS 150 - Spring 2007 – Lec. #11: Course Project - 1Videoconferencing ProjectProject Concept and BackgroundCheckpoint StructureBells and WhistlesCS 150 - Spring 2007 – Lec. #11: Course Project - 2ObjectivesBroad “brush” overview of the projectDetails will be covered in the lab lectures, starting next weekNOTE: anything discussed in the lab lectures and project checkpoint write-ups supercedes what I describe here!Neil and Allen have a working implementation of the projectThey know the project better than I do! Listen to them!CS 150 - Spring 2007 – Lec. #11: Course Project - 3Course Project: Videoconferencing SystemNot quite this… but:Video camera captureCRT video displaySerial compressed video2-way transmission between two stationsWireless communications(no audio this semester)Implemented in a Xilinx FPGA on theCalinx boards in the labGroups of two -- your Lab #4/#5 partnerCommit to a TA now for grading purposesCS 150 - Spring 2007 – Lec. #11: Course Project - 4Calinx EECS 150 Lab/Project ProtoboardFlash Card & Micro-drive PortVideo Encoder & DecoderAC ’97 Codec & Power AmpVideo & Audio PortsFour 100 Mb Ethernet Ports8 Meg x 32SDRAMQuad Ethernet TransceiverXilinxVirtex 2000ESeven Segment LED DisplaysPrototype AreaCS 150 - Spring 2007 – Lec. #11: Course Project - 5Complete Videoconferencing SystemDisplayVideo EncoderVideo Encoder(Checkpoint #1)Video DecoderCameraVideostreamVideoDecod erCheckpoint #2Checkpoint #4SDRAM(Checkpoint #0)Multiport SDRAMMemory SystemMultiportArbitrationWireless Transceiver(Checkpoint #3)CS 150 - Spring 2007 – Lec. #11: Course Project - 6Checkpoint #0/#1/#2: SDRAM InterfaceMemory protocolsBus arbitrationAddress phaseData phaseDRAM is large, but few address lines and slowRow & col addressWait statesSynchronous DRAM provides fast synchronous access current blockLittle like a cache in the DRAMFast burst of dataArbitration for shared resourceCS 150 - Spring 2007 – Lec. #11: Course Project - 7Checkpoint #1: Video EncodingPixel Array:Digital image represented by matrix of values, where each is a function of the information surrounding it in the image; single element in image matrix: picture element or pixel (includes info for all color components)Array size varies for different apps and costs: some common sizes shownFrames: Illusion of motion created by successively flashing still pictures called framesHigh-Definition Television (HDTV), 2 MpxWorkstation, 1 MpxPC/Mac,1‡2 MpxVideo, 300 KpxSIF,82 KpxHigh-Definition Television (HDTV), 1 MpxCS 150 - Spring 2007 – Lec. #11: Course Project - 8Checkpoint #1: Video EncodingVideo details fairly complex and involve many choices:NTSC vs. PAL, HDTV, …Interleaved even-odd frames (TV) vs. progress scan (computer and digital displays)Frame size, frame ratePixel encodings: RGB, YUV/YCB (Luminance, Chrominance -- brightness plus color difference signals)Subsampling to reduce data demands (compression trick)Inputs: ITU-R BT.601 Format (Digital Broadcast NTSC)Outputs: Component video, S-video to drive LCDs in labFortunately, Calinx board has a chip on-board that deals with much of the grungy details …CS 150 - Spring 2007 – Lec. #11: Course Project - 9ITU-R BT.656 DetailsInterfacing details for ITU-601Pixels per line 858Lines per frame 525Frames/sec 29.97Pixels/sec 13.5 MViewable pixels/line 720Viewable lines/frame 487With 4:2:2 chroma sub-sampling, send 2 words/pixel (Cr/Y/Cb/Y)Words/sec = 27MEncoder runs off a 27MHz clockControl info (horizontal & vertical synch) is multiplexed on data linesEncoder data stream show to rightSee video tutorial documents on course documentation web page!718 719 720 721 0 1 2359 360 0 1359 360 0 1736732( )368366()368366()857863)(Y 718Y 719C 360BY 720C 360RY 721C 359BC 359RY 736(732)C 368(366)BC 368(366)RY 855(861)C 428(431)BY 856(862)Y 857(863)C 0BY 0C 0RY 1C 428(431)RC 0BY 0Y 1C 0RC 359BY 718Y 719C 359RLast sampleof digital active lineSample datafor O instantFirst sampleof digital active lineHLuminancedata, YChrominancedata, CRChrominancedata, CBReplaced bytiming referencesignalReplaced bydigital blanking dataReplaced bytiming referencesignalEnd ofactive videoStart ofactive videoTiming reference signalsNote 1 – Sample identification numbers in parentheses are for 625-line systems where these differ from those for 525-line systems. (See also Recommendation ITU-R BT.803.)FIGURE 1Composition of interface data streamD01CS 150 - Spring 2007 – Lec. #11: Course Project - 10Checkpoint #1: Video EncoderDisplay driver processes pixels within frame bufferDrive ADV7194 video encoder device to output correct NTSC videoGain lots of experience reading data sheetsDictates the 27 MHz operation rateUsed throughout graphics subsystemCS 150 - Spring 2007 – Lec. #11: Course Project - 11Calinx On-Board Video EncoderAnalog Devices ADV7194: ITU 601/656 in, Composite Video OutSupports:Multiple input formats and outputsOperational modes, slave/masterUsed in default mode: ITU-601 as slaves-video outputDigital input side connected to Virtex pinsAnalog output side wired to on board connectors or headersI2C interface for initialization:Wired to VirtexCS 150 - Spring 2007 – Lec. #11: Course Project - 12SDRAM READ Burst TimingCS 150 - Spring 2007 – Lec. #11: Course Project - 13Checkpoint #2: Video DecodePretty much the reverse of the encoding process of Checkpoint #1We will provide the base Verilog for video decodeYou will need to integrate video decode with your SDRAM arbitrated write portIntegrate with your Checkpoint #1CS 150 - Spring 2007 – Lec. #11: Course Project - 14Checkpoint #3: Wireless TransceiverThis will involve interfacing to the wireless transceiver chip on the Calinx2 boardNeil working on a clear description of how this worksCS 150 - Spring 2007 – Lec. #11: Course Project - 15Checkpoint
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