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Berkeley COMPSCI 150 - Lecture 3 - Timing

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EECS150 - Digital Design Lecture 3 - TimingOutlineGeneral Model of Synchronous CircuitExample CircuitSlide 5Limitations on Clock RateExampleAnnouncementsQualitative Analysis of Logic DelayGate Switching BehaviorGate DelaySlide 12Wire DelaySlide 14Delay in Flip-flopsSpring 2002 EECS150 - Lec03-TimingPage 1EECS150 - Digital DesignLecture 3 - TimingJanuary 29, 2002John WawrzynekSpring 2002 EECS150 - Lec03-TimingPage 2Outline•General Model of Synchronous Systems–Performance Limits•Announcements•Delay in logic gates•Delay in wires•Delay in flip-flopsSpring 2002 EECS150 - Lec03-TimingPage 3General Model of Synchronous Circuit•All wires, except clock, may be multiple bits wide.•Registers (reg)–collections of flip-flops•clock–distributed to all flip-flops–typical rate?•Combinational Logic Blocks (CL)–no internal state–output only a function of inputs•Particular inputs/outputs are optional•Optional Feedbackr e g r e gC L C Lc l o c k i n p u to u t p u to p t i o n f e e d b a c ki n p u to u t p u tSpring 2002 EECS150 - Lec03-TimingPage 4Example Circuit•Parallel to Serial Converter•All signal paths single bit wide•Registers are single flip-flops•Combinational Logic blocks are simple multiplexors•No feedback.Spring 2002 EECS150 - Lec03-TimingPage 5General Model of Synchronous Circuit•How do we measure performance?–operations/sec?–cycles/sec?•What limits the clock rate?•What happens as we increase the clock rate?r e g r e gC L C Lc l o c k i n p u to u t p u to p t i o n f e e d b a c ki n p u to u t p u tSpring 2002 EECS150 - Lec03-TimingPage 6Limitations on Clock Rate•Logic Gate Delay•What are typical delay values?•Delays in flip-flops•Both times contribute to limiting the clock period.ti n p u to u t p u tDc l kQs e t u p t i m e c l o c k t o Q d e l a y•What must happen in one clock cycle for correct operation?•Assuming perfect clock distribution (all flip-flops see the clock at the same time):–All signals must be ready and “setup” before rising edge of clock.Spring 2002 EECS150 - Lec03-TimingPage 7Example•Parallel to serial converter:T > time(clk->Q) + time(mux) + time(setup) abSpring 2002 EECS150 - Lec03-TimingPage 8Announcements•Lectures now being web-cast and recorded online. URL:•Look at notes online before class. –Suggestion: print out bring copy to class and annotate when necessary. My notes are intentionally incomplete.•Homework #1 online. Turn in before 12 noon Friday.•Discussions, TA office hours, and labs this week.•Quiz Friday at lab lecture.Spring 2002 EECS150 - Lec03-TimingPage 9Qualitative Analysis of Logic Delay•Improved Transistor Model: nFET•We refer to transistor "strength" as the amount of current that flows for a given Vds and Vgs. •The strength is linearly proportional to the ratio of W/L. pFETSpring 2002 EECS150 - Lec03-TimingPage 10Gate Switching Behavior•Inverter:•NAND gate:Spring 2002 EECS150 - Lec03-TimingPage 11Gate Delay•Cascaded gates:V o u tV i nSpring 2002 EECS150 - Lec03-TimingPage 12Gate Delay•Fan-out:•“Fan-in”•What is the delay in this circuit?•Critical DelaySpring 2002 EECS150 - Lec03-TimingPage 13Wire Delay•In general wire behave as “transmission lines”:–signal wave-front moves close to the speed of light•~1ft/ns–In ICs most wires are short, therefore the transit times are relatively short compared to the clock period and can be ignored.–Not so on PC boards.txSpring 2002 EECS150 - Lec03-TimingPage 14Wire Delay•Even in those cases where the transmission line effect is negligible:–Wires posses distributed resistance and capacitance–Time constant associated with distributed RC is proportional to the square of the length–For short wires on ICs, resistance is insignificant (relative to effective R of transistors), but C is important.–Typically around half of C of gate load is in the wires.•For long wires on ICs:–busses, clock lines, global control signal, etc.–distributed RC (and therefore long delay) significant–signals are “rebuffered” to reduce delay:Spring 2002 EECS150 - Lec03-TimingPage 15Delay in Flip-flops•Setup time results delay through first latch.•Clock to Q delay results from delay through second


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Berkeley COMPSCI 150 - Lecture 3 - Timing

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