March 2003 EECS150 - Lec14-cla2Page 1EECS150 - Digital DesignLecture 14 - Combinational Logic & Arithmetic Circuits Part 2March 6, 2003John WawrzynekMarch 2003 EECS150 - Lec14-cla2Page 2Carry Look-ahead Adders• In general, for n-bit addition best we can achieve is delay α log(n)• How do we arrange this? (think trees)• First, reformulate basic adder stage:carry “kill” ki= ai’bi’carry “propagate” pi= ai⊕ bicarry “generate” gi= aibici+1= gi+ picisi= pi⊕ ci0 0 0 0 00 0 1 0 10 1 0 0 10 1 1 1 01 0 0 0 11 0 1 1 01 1 0 1 01 1 1 1 1a b cici+1sMarch 2003 EECS150 - Lec14-cla2Page 3Carry Look-ahead Adders• “Group” propagate and generate signals:• P true if the group as a whole propagates a carry to cout• G true if the group as a whole generates a carry• Group P and G can be generated hierarchically.pigipi+1gi+1pi+kgi+kP = pipi+1… pi+kG = gi+k+ pi+kgi+k-1+ … + (pi+1pi+2… pi+k)gicincoutCout = G + PCinMarch 2003 EECS150 - Lec14-cla2Page 4Carry Look-ahead Addersa0b0a1b1a2b2aa3b3a4b4a5b5bc3= Ga+ Pac0PaGaPbGba6b6a7b7a8b8cc6= Gb+ Pbc3PcGcP = PaPbPcG = Gc+ PcGb+ PbPcGac9= G + Pc0c09-bit Example of hierarchically generated P and G signals:March 2003 EECS150 - Lec14-cla2Page 5c0a0b0s0a1b1s1c1a2b2s2a3b3s3c3c2c0c0a4b4s4a5b5s5c5a6b6s6a7b7s7c7c6c0c4c0c8p,gP,GP,GcincoutP,GPa,GaPb,GbP = PaPbG = Gb+ GaPbCout = G + cinPaibisip,gcici+1p = a ⊕ bg = abs = p ⊕ cici+1 = g + cip8-bit Carry Look-ahead AdderMarch 2003 EECS150 - Lec14-cla2Page 6p0g0s0p1g1s1c1= g0+p0c0p1g2s2c2p3g3s3c3= g2+p2c2p4g4s4p5g5s5p6g6s6c6p7g7s7c0c5= g4+p4c4c7= g6+p6c6c4c2=G8+P8c0P8=p0p1G8=g1+p1g0P9=p2p3c6=Ga+Pac4Pa=p4p5Ga=g5+p5g4Pb=p6p7G9=g3+p3g2Gb=g7+p7g6c4=Gc+Pcc0Pc=P8P9Gc=G9+P9G8Pd=PaPbGd=Gb+PbGac8=Ge+Pec0Pe=PcPdGe=Gd+PdGcc0c4c88-bit Carry Look-ahead Adder with 2-input gates.March 2003 EECS150 - Lec14-cla2Page 7Carry look-ahead Wrap-up• Adder delay α log2N (up then down the tree). •Cost?• Can be applied with other techniques. Group P & G signals can be generated for sub-adders, but another carry propagation technique (for instance ripple) used within the group.• Other more complex techniques exist that can bring the delay down below O(logN), but are only efficient for very wide adders.March 2003 EECS150 - Lec14-cla2Page 8Bit-serial Adder• Addition of 2 n-bit numbers:– takes n clock cycles,– uses 1 FF, 1 FA cell, plus registers– the bit streams may come from or go to other circuits, thereforethe registers may be optional.• A, B, and R held in shift-registers. Shift right once per clock cycle.• Reset is asserted by controller.n-bit shift registern-bit shift registersscresetRFAFFBAMarch 2003 EECS150 - Lec14-cla2Page 9Adders on the Xilinx Virtex• Dedicated carry logic provides fast arithmetic carry capability for high-speed arithmetic functions. The Virtex-E CLB supports two separate carry chains, one per Slice. The height of the carry chains is two bits per CLB.• The arithmetic logic includes an XOR gate and AND gate that allows a 2-bit full adder to be implemented within a slice. • Cin to Cout delay = 0.1ns, versus 0.4ns for F to X delay.How do we map a 2-bit adder to one slice?March 2003 EECS150 - Lec14-cla2Page 10Multiplicationa3a2a1a0Multiplicandb3b2b1b0MultiplierXa3b0a2b0a1b0a0b0a3b1a2b1a1b1a0b1Partiala3b2a2b2a1b2a0b2productsa3b3a2b3a1b3a0b3 . . . a1b0+a0b1a0b0ProductMany different circuits exist for multiplication.Each one has a different balance between speed (performance) and amount of logic (cost).March 2003 EECS150 - Lec14-cla2Page 11“Shift and Add” Multiplier• Sums each partial product, one at a time.• In binary, each partial product is shifted versions of A or 0.Control Algorithm:1. P ← 0, A ← multiplicand, B ← multiplier2. If LSB of B==1 then add A to Pelse add 03. Shift [P][B] right 14. Repeat steps 2 and 3 n-1 times.5. [P][B] has product.Bn-bit shift registersPAn-bit register+010 n-bit adder•Cost α n, Τ = n clock cycles.• What is the critical path for determining the min clock period?March 2003 EECS150 - Lec14-cla2Page 12“Shift and Add” MultiplierSigned Multiplication:Remember for 2’s complement numbers MSB has negative weight:ex: -6 = 110102= 0•20+ 1•21+ 0•22+ 1•23-1•24= 0 + 2 + 0 + 8 - 16 = -6• Therefore for multiplication:a) subtract final partial productb) sign-extend partial products• Modifications to shift & add circuit:a) adder/subtractorb) sign-extender on P shifter register 112022−−−=−=∑nniNiixxXMarch 2003 EECS150 - Lec14-cla2Page 13Array Multiplierb3 0 b2 0 b1 0 b0 0P7 P6 P5 P4a00a10a20a30P0P1P2P3FAbjsum insum outcarryoutaicarryinEach row: n-bit adder with AND gatesWhat is the critical path?Generates all n partial products simultaneously.March 2003 EECS150 - Lec14-cla2Page 14Carry-save Addition• Speeding up multiplication is a matter of speeding up the summing of the partial products.• “Carry-save” addition can help.• Carry-save addition passes (saves) the carries to the output, rather than propagating them.• Example: sum three numbers,310= 0011, 210= 0010, 310= 00113100011+ 2100010c 0100 = 410s 0001 = 1103100011c 0010 = 210s 0110 = 6101000 = 810carry-save addcarry-save addcarry-propagate add• In general, carry-save addition takes in 3 numbers and produces 2.• Whereas, carry-propagate takes 2 and produces 1.• With this technique, we can avoid carry propagation until final additionMarch 2003 EECS150 - Lec14-cla2Page 15Carry-save Circuits• When adding sets of numbers, carry-save can be used on all but the final sum.• Standard adder (carry propagate) is used for final sum.FAFAFA FAFA FA FA FA0CSAs cs cs cs cs cs cs cs ccCSACPACSACSAx0x1x2March 2003 EECS150 - Lec14-cla2Page 16Array Multiplier using Carry-save Additionb3 0 b2 0 b1 0 b0 0P7 P6 P5 P4a00a1a2a3P0P1P2P310000000000FAbjsum insum outcarryoutaicarryinFast carry-propagate adderMarch 2003 EECS150 - Lec14-cla2Page 17Carry-save AdditionCSA is associative and communitive. For example:(((X0 + X1)+X2 )+X3 ) = ((X0 + X1)+(X2 +X3 ))• A balanced tree can be used to reduce the logic delay.• This structure is the basis of the Wallace Tree Multiplier.• Partial products are summed with the CSA tree. Fast CPA (ex: CLA) is used for final sum.• Multiplier delay α log3/2N +
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