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Berkeley COMPSCI 150 - Lecture 12 - Timing

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EECS 150 - Components and Design Techniques for Digital Systems Lec 12 - TimingOutlineRecall: General Model of Synchronous CircuitGeneral Model of Synchronous CircuitLimitations on Clock RateExample: Parallel-Serial ConverterSlide 7Recall L2: Transistor-level Logic CircuitsQualitative Analysis of Logic DelayGate Switching BehaviorClarify your understandingDelays in a series of gatesGate Delay due to fan outGate Delay with a general circuitWhat is the delay through arbitrary combinational logic?AnnouncementsDelay in Flip-flopsWire DelayArchitectural Level DelaySlide 20Modern rule of thumbClock SkewClock Skew ConstraintsHacking Clock SkewTime to ask clarifying questionsOther effects of Delays on Combinational LogicTime Behavior of Combinational NetworksMomentary Changes in OutputsOscillatory BehaviorHazards/GlitchesTypes of HazardsStatic HazardsDynamic HazardsSlide 34Eliminating Static HazardsEliminating Dynamic HazardsProtocolsOur old friend…Simple Protocol ExampleAnother Protocol ExampleSummary10-4-2007Lec12 EECS150 Fa071EECS 150 - Components and Design Techniques for Digital Systems Lec 12 - Timing David CullerElectrical Engineering and Computer SciencesUniversity of California, Berkeleyhttp://www.eecs.berkeley.edu/~cullerhttp://www-inst.eecs.berkeley.edu/~cs15010-4-2007Lec12 EECS150 Fa072Outline•Performance Limits of Synchronous Systems•Delay in logic gates•Delay in wires•Delay in combinational networks•Clock Skew•Delay in flip-flops•Glitches10-4-2007Lec12 EECS150 Fa073Recall: General Model of Synchronous Circuit•All wires, except clock, may be multiple bits wide.•Registers (reg)–collections of flip-flops•clock–distributed to all flip-flops–typical rate?•Combinational Logic Blocks (CL)–no internal state–output only a function of inputs•Particular inputs/outputs are optional•Optional Feedbackr e g r e gC L C Lc l o c k i n p u to u t p u to p t i o n f e e d b a c ki n p u to u t p u t10-4-2007Lec12 EECS150 Fa074General Model of Synchronous Circuit•How do we measure performance?–operations/sec?–cycles/sec?•What limits the clock rate?•What happens as we increase the clock rate?r e g r e gC L C Lc l o c k i n p u to u t p u to p t i o n f e e d b a c ki n p u to u t p u t10-4-2007Lec12 EECS150 Fa075Limitations on Clock Rate1Logic Gate Delay•What are typical delay values?2Delays in flip-flops•Both times contribute to limiting the clock period.ti n p u to u t p u tDc l kQs e t u p t i m e c l o c k t o Q d e l a y•What must happen in one clock cycle for correct operation?•Assuming perfect clock distribution (all flip-flops see the clock at the same time):–All signals must be ready and “setup” before rising edge of clock.10-4-2007Lec12 EECS150 Fa076Example: Parallel-Serial ConverterabT  time(clkQ) + time(mux) + time(setup)T  clkQ + mux + setupclk10-4-2007Lec12 EECS150 Fa077General Model of Synchronous Circuit•In general, for correct operation:for all paths.•How do we enumerate all paths?–Any circuit input or register output to any register input or circuit output.–“setup time” for circuit outputs depends on what it connects to–“clk-Q time” for circuit inputs depends on from where it comes.r e g r e gC L C Lc l o c k i n p u to u t p u to p t i o n f e e d b a c ki n p u to u t p u tT  time(clkQ) + time(CL) + time(setup)T  clkQ + CL + setup10-4-2007Lec12 EECS150 Fa078Recall L2: Transistor-level Logic Circuits•Inverter (NOT gate):VddGndVddGnd0 voltsin out3 voltswhat is the relationship between in and out?10-4-2007Lec12 EECS150 Fa079Qualitative Analysis of Logic Delay•Improved Transistor Model: •We refer to transistor "strength" as the amount of current that flows for a given Vds and Vgs. •The strength is linearly proportional to the ratio of W/L–Physical property•Turn it on harder allows more current to flowpFETnFETWhat is the effective resistance?10-4-2007Lec12 EECS150 Fa0710Gate Switching Behavior•Inverter:•NAND gate:gsdsWhen does it start? How quickly does it switch?10-4-2007Lec12 EECS150 Fa0711Clarify your understandingWhat is the 0  1 and 1  0 behavior of a NOR gate?Why do we need pMOS and nMOS devices in a pass gate? - used for tristate10-4-2007Lec12 EECS150 Fa0712Delays in a series of gates•Cascaded gates:V o u tV i n10-4-2007Lec12 EECS150 Fa0713Gate Delay due to fan out•Fan-out:•The delay of a gate is proportional to its output capacitance. Because, gates #2 and 3 turn on/off at a later time. (It takes longer for the output of gate #1 to reach the switching threshold of gates #2 and 3 as we add more output capacitance.)13210-4-2007Lec12 EECS150 Fa0714Gate Delay with a general circuit•“Fan-in”–Does it affect the delay of the individual gate?–When does the gate begin its transition?•What is the delay in this circuit?•Critical Path: the path with the maximum delay, from any input to any output.–In general, we include register set-up and clk-to-Q times in critical path calculation.•Why do we care about the critical path?10-4-2007Lec12 EECS150 Fa0715What is the delay through arbitrary combinational logic?10-4-2007Lec12 EECS150 Fa0716Announcements•Reading: K&B 3.5 6.1.5-6.2.3 (were in 9/20 assignment)•K&B 10.6 is great protocol example–We’ll do several of those as we go•HW 5 out today (due 10/12)•Class survey•Lab partners10-4-2007Lec12 EECS150 Fa0717Delay in Flip-flops•Setup time results from delay through first latch.•Clock to Q delay results from delay through second latch.Dc l kQs e t u p t i m e c l o c k t o Q d e l a yclkclk’clkclkclk’clk’clkclk’10-4-2007Lec12 EECS150 Fa0718Wire Delay•In general, wire behave as “transmission lines”:–signal wave-front moves close to the speed of light»~1ft/ns–Time from source to destination is called the “transit time”.–In ICs most wires are short, and the transit times are relatively short compared to the clock period and can be ignored.–Not so on PC boards.–...Or long wires on fast chips»Busses»Global Control signals»Clock•Rule of thumb: wire must be treated as a transmission line if its length exceed /100.tx10-4-2007Lec12 EECS150 Fa0719Architectural Level DelaydatapathControllerData bussesclock10-4-2007Lec12 EECS150 Fa0720Wire Delay•Even in those cases where the transmission line effect is negligible:–Wires posses distributed resistance and capacitance–Time constant associated with


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Berkeley COMPSCI 150 - Lecture 12 - Timing

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