SR_SPS1 PS0 X NS1 NS09/7 & 9/9CS150Section week 21. FSMs ( Finite State Machines ) Moore machines: Diagram 1) Outputs depend on:2) Outputs change:Mealy machines1) Outputs depend on:2) Outputs change:Generic steps for designing an FSM:1)2) ( )3)4)5)6)7)2. FSM Example: A rising edge detector Design a finite state machine which takes a bitstream as input, outputting a single high pulse when the input changes from low to high.Mealy Moore1) 1)2) 2)3) Mealy 3) Moore4) 4)CLKINRE CLK IN REMealy Moore5) 5)6) 6)2. Backwards FSM design example: Meaningless random circuitGeneric steps for obtaining STD from logic equations –1)2)3)Circuit description:Given an FSM consisting of two D flip-flops and an input X, generate the corresponding STT & STD. The next state equations are: ___ __ ___NS1 = X PS1 PS0 + X PS1 + PS1 PS0 __NS0 = XSTT STDPS1 PS0 X NS1 NS00 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 13. Cross coupled NAND gates_S_RQQ’Unit Time: 0 1 2 3 4 5 6 7 8 9 10 11 1210101010__S__RQ’Q _ _ S R Q0 00 11 01
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