Department of Electrical Engineering and Computer SciencesLab 3FPGA CAD Tool Flow1 Motivation2 Prelab3 Procedure3.1 Getting Started3.2 Simulate the DesignUsage: w “name”3.3 Implementing the design3.4 Analyzing implementation, Timing Analyzer3.5 Analyzing implementation, Floor Planner3.6 Analyzing implementation, FPGA Editor3.7 Download the circuit3.8 Observe the circuit in operation4 AcknowledgementOriginal lab by J. Wawryznek, N. Zhou.Prelab QuestionsQuestions5 CheckoffsEECS150 Spring 2002 Lab3 FPGA CAD Tool FlowUniversity of California at BerkeleyCollege of EngineeringDepartment of Electrical Engineering and Computer SciencesLab 3FPGA CAD Tool Flow1 MotivationIn this lab you will be using the Xilinx FPGA CAD tool flow from design entry toprogramming the hardware. The goal for this lab is to familiarize yourself with the software thatyou’ll be using for the rest of the semester. 2 Prelab1. Examine the circuit that we have provided for you and find out its function. Pictures ofthe circuit will be posted on the website http://inst.eecs.berkeley.edu/~cs150/labs/lab3/.2. Come up with a testing strategy for this circuit.3. Skim over “Foundation Series 3.1i Quick Start Guide” in the Xilinx CAD tooldocumentations. http://toolbox.xilinx.com/docsan/3_1i/docscan.htm 3 Procedure3.1 Getting StartedFirst step in the tool flow after you have conceptualized your circuit is design entry. Forthis lab we just want to familiarize you with the tool flow so we have already entered a circuit foryou. To get the design files:- Extract Lab3.zip from \\fileservice\cs150\cs150\lab3\ into your home directory.(Note your home directory should be a mounted networked drive under My Computer)- Run Project Manager (from desk top)- Open the project called lab3 from the directory where you extracted the files.Open up the schematic of the design by double clicking the .sch file under the file tab onthe left side of the screen. The design is done hierarchically; this means that many of the symbolsare composed of smaller pieces. To view the sub-components of a module right click on it andchoose hierarchical push.3.2 Simulate the Design UCB 1 1/14/2019EECS150 Spring 2002 Lab3 FPGA CAD Tool FlowOnce a design is entered, its functionality should be verified. The Xilinx tool suiteprovides a simulator for the netlist that is generated from your design. Launch the simulator byclicking on the button in the simulation box. Use your testing strategy to verify the functionalityof the circuit.You can control the simulation by typing commands in the command window. Here aresome useful commands to help you get started with the simulation. (The full list of commandscan be found in Tools->Script editor, Tools->macro assistant)vector or v, adds a collection of wires to the simulator. Usage: v “name” “list of wires”Example: v input_bus input[7:0]assign or a, assigns a value to a signal or collection of signals.Usage: a “name” “value”Example: a input_bus 3f\h watch or w, adds an individual signal to the simulation.Usage: w “name”Example: w resethigh or h, low or l, assigns a value of 1 or 0 to a single signal.Usage: h “name”Example: h resetclock, assign a signal to repeat a set pattern.Usage: clock “name” “pattern”Example: clock clk 0 1cycle or c, advance the simulation time by n clock cycles.Usage: c “n”Example: c 10 (note: just typing c defaults to one cycle)If you wish to reuse the same commands many times you can enter the list of commandsin a text file, you can use the script editor provided by the tools or just note pad to do this. Showyour TA your simulations of the design.3.3 Implementing the designThe next step in the tool flow is implementing your design. This involves translating,mapping, placement, routing, and bit-file generation. The Xilinx tool suite merged these stepsinto a tool called Flow Engine.The Xilinx Flow Engine takes (EDIF) a netlist generated fromyour design and compiles into a bit file that can be downloaded to the Xilinx chip.Start the Flow Engine by clicking on the Implementation box (located under the DesignEntry box). In the dialog box that comes up after clicking on Implementation, set the Device to4010XLPC84, and Speed of 1. Then run. A new window will pop up showing the progress ofthe compilation and routing. To look at the results of the compilation, click on the “Versions” tabin your project manager. Right click on the revision that you need information on, and select“View Implementation Log” or “Invoke Interactive Flow Engine”. Both will show you a logof the compilation. You can also access the log by clicking on the “Reports” tab and doubleclicking on “Implementation Log File”. Look through the log files. They provide informationsuch as the amount of FPGA resources that your design uses (LUTs, Flip-Flops, CLBs, IO pads, UCB 2 1/14/2019EECS150 Spring 2002 Lab3 FPGA CAD Tool FlowClock buffer…), the estimated clock speed that your design can operate at, and all the error andwarning messages.3.4 Analyzing implementation, Timing AnalyzerIncluded in the Xilinx tool suite is a “static timing analyzer” that will automatically findthe path delays in your implemented design. This tool is useful in a performance sensitive designwhere knowing the critical path will help in optimizing circuit performance.Start the timing analyzer by click on the Timing Analyzer button under Verification.Once the timing analyzer is launched choose Report path and timing constraints, select reportunconstrained paths then proceed. Take a look at the generated timing report. What is the delayof the critical path in this design? How many levels of logic does it have? Try tracing the criticalpath in the schematic file. (Hint: if you highlight components and wires in the schematic theirname will show up at the bottom of the schematic editor. You’ll also need to use hierarchicalpush to look inside of the modules)3.5 Analyzing implementation, Floor PlannerThe floor planner tool provides a way for the user the manually choose the placement ofsome or all of the design onto the FPGA. For certain kinds of designs where speed is critical it ispreferable to hand place part of your design to obtain higher performance. Select Tools->Implementation->Floor Planner, to see the current placement of the resources.
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