Spring 2010EECS150 - Lec05-VerilogPage EECS150 - Digital DesignLecture 5 - Verilog IntroductionFeb 2, 2010John Wawrzynek1Spring 2010EECS150 - Lec05-VerilogPage Outline• Background and History of Hardware Description• Brief Introduction to Verilog Basics• Lots of examples– structural, data-flow, behavioral• Verilog in EECS1502Spring 2010EECS150 - Lec05-VerilogPage Design Entry• Schematic entry/editing used to be the standard method in industry and universities.• Used in EECS150 until 2002Schematics are intuitive. They match our use of gate-level or block diagrams.Somewhat physical. They imply a physical implementation.Require a special tool (editor).Unless hierarchy is carefully designed, schematics can be confusing and difficult to follow on large designs.• Hardware Description Languages (HDLs) are the new standard– except for PC board design, where schematics are still used.3Spring 2010EECS150 - Lec05-VerilogPage Hardware Description Languages• Basic Idea:– Language constructs describe circuits with two basic forms:–Structural descriptions: connections of components. Nearly one-to-one correspondence to with schematic diagram.–Behavioral descriptions: use high-level constructs (similar to conventional programming) to describe the circuit function.• Originally invented for simulation.– Now “logic synthesis” tools exist to automatically convert from HDL source to circuits.– High-level constructs greatly improves designer productivity.– However, this may lead you to falsely believe that hardware design can be reduced to writing programs!*“Structural” example:Decoder(output x0,x1,x2,x3; inputs a,b){ wire abar, bbar; inv(bbar, b); inv(abar, a); and(x0, abar, bbar); and(x1, abar, b ); and(x2, a, bbar); and(x3, a, b );} “Behavioral” example:Decoder(output x0,x1,x2,x3; inputs a,b){ case [a b] 00: [x0 x1 x2 x3] = 0x1; 01: [x0 x1 x2 x3] = 0x2; 10: [x0 x1 x2 x3] = 0x4; 11: [x0 x1 x2 x3] = 0x8; endcase;} 4Warning: this is a fake HDL!*Describing hardware with a language is similar, however, to writing a parallel program.Spring 2010EECS150 - Lec05-VerilogPage Sample Design MethodologyHDLSpecificationHierarchically defines structure and/or function of circuit.SimulationVerification: Does the designbehave as required with regards to function, timing, and power consumption?SynthesisMaps specification to resources of implementation platform (FPGA or custom silicon).5Note: This in not the entire story. Other tools are useful for analyzing HDL specifications. More on this later.Spring 2010EECS150 - Lec05-VerilogPage Verilog• A brief history:– Originated at Automated Integrated Design Systems (renamed Gateway) in 1985. Acquired by Cadence in 1989.– Invented as simulation language. Synthesis was an afterthought. Many of the basic techniques for synthesis were developed at Berkeley in the 80’s and applied commercially in the 90’s.– Around the same time as the origin of Verilog, the US Department of Defense developed VHDL (A double acronym! VSIC (Very High-Speed Integrated Circuit) HDL). Because it was in the public domain it began to grow in popularity.– Afraid of losing market share, Cadence opened Verilog to the public in 1990. – An IEEE working group was established in 1993, and ratified IEEE Standard 1394 (Verilog) in 1995. We use IEEE Std 1364-2001.– Verilog is the language of choice of Silicon Valley companies, initially because of high-quality tool support and its similarity to C-language syntax.– VHDL is still popular within the government, in Europe and Japan, and some Universities.– Most major CAD frameworks now support both.– Latest Verilog version is “system Verilog” .– Latest HDL: C++ based. OSCI (Open System C Initiative).6Spring 2010EECS150 - Lec05-VerilogPage Verilog Introduction•A module definition describes a component in a circuit• Two ways to describe module contents:– Structural Verilog• List of sub-components and how they are connected• Just like schematics, but using text• tedious to write, hard to decode• You get precise control over circuit details• May be necessary to map to special resources of the FPGA– Behavioral Verilog• Describe what a component does, not how it does it• Synthesized into a circuit that has this behavior• Result is only as good as the tools• Build up a hierarchy of modules. Top-level module is your entire design (or the environment to test your design).7Spring 2010EECS150 - Lec05-VerilogPage Verilog Modules and Instantiation•Modules define circuit components. •Instantiation defines hierarchy of the design.module addr_cell (a, b, cin, s, cout); input a, b, cin; output s, cout; endmodule8Note: A module is not a function in the C sense. There is no call and return mechanism. Think of it more like a hierarchical data structure. name port listport declarations (input, output, or inout)module bodymodule adder (A, B, S); addr_cell ac1 ( ); endmoduleInstance of addr_cell... connections ...keywordsSpring 2010EECS150 - Lec05-VerilogPage module xor_gate ( out, a, b ); input a, b; output out; wire aBar, bBar, t1, t2; not invA (aBar, a); not invB (bBar, b); and and1 (t1, a, bBar); and and2 (t2, b, aBar); or or1 (out, t1, t2);endmoduleStructural Model - XOR example–Notes: • The instantiated gates are not “executed”. They are active always.• xor gate already exists as a built-in (so really no need to define it).• Undeclared variables assumed to be wires. Don’t let this happen to you!port listmodule nameport declarationsinstancesBuilt-in gatesInstance nameInterconnections (note output is first)9outinternal signal declarationsSpring 2010EECS150 - Lec05-VerilogPage Structural Example: 2-to1 mux/* 2-input multiplexor in gates */module mux2 (in0, in1, select, out); input in0,in1,select; output out; wire s0,w0,w1; not (s0, select); and (w0, s0, in0), (w1, select, in1); or (out, w0, w1);endmodule // mux210C++ style commentsMultiple instances can share the same “master” name.and (w0, a, b, c, d);Built-ins gates can have > 2 inputs. Ex:Built-ins don’t need Instance namesSpring 2010EECS150 - Lec05-VerilogPage Instantiation, Signal Array, Named ports11module mux4 (in0, in1, in2, in3, select, out); input in0,in1,in2,in3; input [1:0] select; output out; wire w0,w1; mux2 m0 (.select(select[0]), .in0(in0), .in1(in1),
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