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Berkeley COMPSCI 150 - SECTION 4 - Finite State Machines

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EECS150Section 4Finite State MachinesFall 2001EECS150 - Fall 2001 1-2Abstraction of State ElementsDivide circuit into combinational logic and stateLocalize feedback loops and make it easy to break cyclesImplementation of storage elements leads to various forms of sequential logicCombinationalLogicStorage ElementsOutputsState OutputsState InputsInputsEECS150 - Fall 2001 1-3In = 0In = 1In = 0In = 1100010110111001Finite State Machine RepresentationStates: determined by possible values in sequential storage elementsTransitions: change of stateClock: controls when state can change by controlling storage elementsSequential LogicSequences through a series of statesBased on sequence of values on input signalsClock period defines elements of sequenceEECS150 - Fall 2001 1-4Pieces of FSMsDQNex tstateDecoder/ //new value forpresentinputscomb. logicst atenext stateNSDDecoder/ //outp utsP.S .inpu tscomb. logicODOutput/ /State registernext state to loadon rising edgeclockpresentstateEECS150 - Fall 2001 1-5Types of FSM’sMoore and Mealey FSMclockQDNSDinpu ts/OD /Mo oreclockQDNSDinputsOD/Mealey/PSNSoutputsoutp ut sfun ction only ofpresent stateEECS150 - Fall 2001 1-6Example Finite State MachineCombination lock from first lectureresetS3closedclosedmux=C1equal& newnot equal& newnot equal& newnot equal& newnot newnot newnot newS1 S2 OPENERRclosedmux=C2equal& newclosedmux=C3equal& newopenEECS150 - Fall 2001 1-7Shift Registers as FSM’sShift RegisterInput value shownon transition arcsOutput values shownwithin state node1001101110111010100000010111111100000100DQ DQ DQINOUT1 OUT2 OUT3CLKEECS150 - Fall 2001 1-80101001100110010001011113-bit up-counterCounters as FSM’sCountersProceed thru well-defined state sequence in response to enableMany types of counters: binary, BCD, Gray-code3-bit up-counter: 000, 001, 010, 011, 100, 101, 110, 111, 000, ...3-bit down-counter: 111, 110, 101, 100, 011, 010, 001, 000, 111, ...EECS150 - Fall 2001 1-9Turn a State Diagram into LogicCounterThree flip-flops to hold stateLogic to compute next stateClock signal controls when flip-flop memory can changeWait long enough for combinational logic to compute new valueDon't wait too long as that is low performanceDQ DQ DQOUT1 OUT2 OUT3CLK"1"EECS150 - Fall 2001 1-100101001100110010001011113-bit up-countercurrent state next state0 000 001 11 001 010 22 010 011 33 011 100 44 100 101 55 101 110 66 110 111 77 111 000 0State Transition TableTabular form of state diagramLike a truth-table (specify output for all input combinations)Encoding of states: easy for counters – just use valueN1 := C1'N2 := C1C2' + C1'C2:= C1 xor C2N3 := C1C2C3' + C1'C3 + C2'C3:= C1C2C3' + (C1' + C2')C3:= (C1C2) xor C3EECS150 - Fall 2001 1-11D QQImplementationProgrammable Logic Building Block for Sequential LogicMacro-cell: FF + logicD-FFTwo-level logic capability like PAL (e.g., 8 product terms)EECS150 - Fall 2001 1-12In C1 C2 C3 N1 N2 N30000000000100000100010011001010001001010100110011011101110001001001100101010110111011100110110111011101111111111N1 := InN2 := C1N3 := C2Another ExampleShift RegisterInput determines next state1001101110111010100000010111111100000100DQ DQ DQINOUT1 OUT2 OUT3CLKEECS150 - Fall 2001 1-13State Machine ModelValues stored in registers represent the state of the circuitCombinational logic computes:Next stateFunction of current state and inputsOutputsFunction of current state and inputs (Mealy machine)Function of current state only (Moore machine)InputsOutputsNext StateCurrent Stateoutputlogicnext statelogicEECS150 - Fall 2001 1-14State Machine Model (cont’d)States: S1, S2, ..., SkInputs: I1, I2, ..., ImOutputs: O1, O2, ..., OnTransition function: Fs(Si, Ij)Output function: Fo(Si) or Fo(Si, Ij)InputsOutputsNext StateCurrent Stateoutputlogicnext statelogicClockNext StateState012345EECS150 - Fall 2001 1-15D/1E/1B/0A/0C/01000011110resetcurrent nextreset input state state output1–– A00A B 001A C 000B B 001B D 000C E 001C C 000D E 101D C 100E B 101E D 1Specifying Outputs: Moore MachineOutput is only function of state Specify in state bubble in state diagram Example: sequence detector for 01 or 10EECS150 - Fall 2001 1-16current nextreset input state state output1–– A 000A B 001A C 000B B 001B C 100C B 101C C 0BAC0/10/00/01/11/01/0reset/0Specifying Outputs: Mealy MachineOutput is function of state and inputs Specify output on transition arc between states Example: sequence detector for 01 or 10EECS150 - Fall 2001 1-17state feedbackinputsoutputsregcombinational logic for next statelogic foroutputsinputs outputsstate feedbackregcombinational logic fornext statelogic foroutputsComparison: Mealy/Moore MachinesMealy Machines tend to have less statesDifferent outputs on arcs (n^2) rather than states (n)Moore Machines are safer to useOutputs change at clock edge (always one cycle later)In Mealy machines, input change can cause output change as soon as logic is done – a big problem when two machines are interconnected – asynchronous feedbackMealy Machines react faster to inputsReact in same cycle – don't need to wait for clockIn Moore machines, more logic may be necessary to decode state into outputs – more gate delays after EECS150 - Fall 2001 1-18DQQBAclockoutDQQDQQclockoutABMealy and Moore ExamplesRecognize A,B = 0,1 Mealy or Moore?EECS150 - Fall 2001 1-19DQQDQQDQQDQQABclockoutDQQDQQABclockoutMealy and Moore ExamplesRecognize A,B = 1,0 then 0,1 Mealy or Moore?EECS150 - Fall 2001 1-20Registered Mealy (Really Moore)Synchronous (or registered) Mealy MachineRegistered state AND outputsAvoids ‘glitchy’ outputsEasy to implement in PLDsMoore Machine with no output decodingOutputs computed on transition to next state rather than after enteringView outputs as expanded state vectorInputsOutputsCurrent Stateoutputlogicnext statelogicEECS150 - Fall 2001 1-21Example: Ant Brain (Ward, MIT)Sensors: L and R antennae, 1 if in touching wallActuators: F - forward step, TL/TR - turn left/right slightlyGoal: find way out of mazeStrategy: keep the wall on the rightEECS150 - Fall 2001 1-22A: Following wall, touching Go forward, turning left slightlyB: Following wall, not touching Go forward, turning right slightlyC: Break in wall Go forward, turning right slightlyD: Hit wall again Back to state AE: Wall in


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Berkeley COMPSCI 150 - SECTION 4 - Finite State Machines

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