UC Regents Spr 2010 © UCBEECS 150 - L11: Processor Pipelining2010-2-23John WawrzynekEECS 150 -- Digital DesignLecture 11-- Processor Pipeliningwww-inst.eecs.berkeley.edu/~cs150Today’s lecture by John Lazzaro1UC Regents Spr 2010 © UCBEECS 150 - L11: Processor PipeliningToday: PipeliningHow to apply the performance equation to our single-cycle CPU. Why pipelining is hard: data hazards,control hazards, structural hazards.Pipelining: an idea from assemblyline production applied to CPU designVisualizing pipelines to evaluatehazard detection and resolution.A tool kit for hazard resolution.2UC Regents Spr 2010 © UCBEECS 150 - L11: Processor PipeliningNew successful instruction sets are rareinstruction setsoftwarehardwareImplementors suffer with original sins of ISAs, to support the installed base of software.3UC Regents Spr 2010 © UCBEECS 150 - L11: Processor Pipeliningdefine: The Architect’s ContractTo the program, it appears that instructions execute in the correct order defined by the ISA.What the machine actually does is up to the hardware designers, as long as the contract is kept.As each instruction completes, themachine state (regs, mem) appears to the program to obey the ISA.Goal: Keep contract and run programs faster.4UC Regents Spr 2010 © UCBEECS 150 - L11: Processor PipeliningPerformance Measurement(as seen by a CPU designer)Q. Why do we care about a program’s performance?A. We want the CPU we are designing to run it well !5UC Regents Spr 2010 © UCBEECS 150 - L11: Processor PipeliningStep 1: Analyze the right measurement!CPU Time:Time the CPU spends running program under measurement.Response Time:Total time: CPU Time + time spent waiting (for disk, I/O, ...).Guides CPU designGuides system design Measuring CPU time (Unix):% time <program name>25.77u 0.72s 0:29.17 90.8% 6UC Regents Spr 2010 © UCBEECS 150 - L11: Processor Pipelining CPU time: Proportional to Instruction CountCPU timeProgramMachine InstructionsProgramRationale: Every additional instruction you execute takes time.Q. How does an architect influence the number of machine instructions needed to run an algorithm?A. Create new instructions:instruction set architect.Q. Static count?(lines of program printout)Or dynamic count? (trace of execution)A. Dynamic.Q. Once ISA is set, who can influence instructioncount?A. Compiler writer,application developer.7UC Regents Spr 2010 © UCBEECS 150 - L11: Processor Pipelining CPU time: Proportional to Clock PeriodTimeProgramTimeOne Clock PeriodQ. What ultimately limitsan architect’s ability to reduce clock period ?A. Clock-to-Q, setup times.Q. How can architects (not technologists) reduce clock period?A. Shorten the machine’s critical path.Rationale: We measure each instruction’sexecution time in “number of cycles”. By shortening the period for each cycle, we shorten execution time.8UC Regents Spr 2010 © UCBEECS 150 - L11: Processor Pipelining Completing the performance equationSecondsProgram InstructionsProgram=SecondsCycleWe need all three terms, and only these terms, to compute CPU Time!When is it OK to compare clock rates?What factors make different programs have different CPIs? Instruction mix varies.Cache behavior varies.Branch prediction varies.“CPI” -- The Average Number of Clock Cycles Per Instruction For the Program InstructionCycles9UC Regents Spr 2010 © UCBEECS 150 - L11: Processor PipeliningConsider Lecture 10 single-cycle CPU ...All instructions take 1 cycle to execute every time they run.CPI of any program running on machine?1.0“average CPI for the program” is a more-useful concept for more complicated machines ...10UC Regents Spr 2010 © UCBEECS 150 - L11: Processor Pipelining Consider machine with a data cache ... InstructionsProgram=SecondsCycleA program’s load instructions “stride” through every memory address.The cache never “hits”, so every load goes to DRAM (100x slower than loads that go to cache). Thus, the average number of cycles for load instructions is higher for this program. InstructionCyclesThus, the average number of cycles for all instructions is higher for this program.SecondsProgramThus, program takes longer to run!11UC Regents Spr 2010 © UCBEECS 150 - L11: Processor Pipelining Final thoughts: Performance EquationSecondsProgram InstructionsProgram=SecondsCycle InstructionCyclesGoal is to optimize execution time, notindividualequationterms.The CPI of the program.Reflectsthe program’s instruction mix.Machinesareoptimizedwith respect toprogramworkloads.Clockperiod.OptimizejointlywithmachineCPI.12UC Regents Spr 2010 © UCBEECS 150 - L11: Processor PipeliningPipelining13UC Regents Spr 2010 © UCBEECS 150 - L11: Processor PipeliningClocking methodology ...Processor uses synchronous logicdesign (a “clock”).!"#$%&'())* ++,!-.)'/ 012-)34$5$%&67&1'8!"#$%&'( )#*#&&'&+,-+.'*/#&+0-12'*,'*3+#45+! ,/$'60&7"89+:+,/$'6$;"9+:+,/$'6.',;%95+! #0&7"8:+#$;":+#.',;%0&7fT1 MHz1 μs10 MHz100 ns100 MHz10 ns1 GHz1 nsAll state elements act like positive edge-triggered flip flops.D Qclk14UC Regents Spr 2010 © UCBEECS 150 - L11: Processor PipeliningMemory and register file semantics ...32rd1RegFile32rd2WE32wd5rs15rs25wsReads are combinational: Put a stable address on input, a short time later data appears on output. 32DoutData MemoryWE32Din32AddrWrites are clocked: If WE is high, memory Addr (or register file ws) captures memory Din (or register file wd) on positive edge of clock.Note: May not be best choice for project.15UC Regents Spr 2010 © UCBEECS 150 - L11: Processor PipeliningRecall: A single-cycle processorrd1RegFilerd2WEwdrs1rs2wsDPCQ+0x4DoutData MemoryWEDinAddrMemToRegAddr DataInstrMem32ALU3232opExtSecondsProgram InstructionsProgram=SecondsCycle InstructionCyclesCPI == 1This is good.Slow.This is bad.Challenge: Speed up clock while keeping CPI == 116UC Regents Spr 2010 © UCBEECS 150 - L11: Processor Pipelining A MIPS R-format CPU design32rd1RegFile32rd2WE32wd5rs15rs25ws32ALU3232opopcode rs rt rd functshamtDecode fields to get : ADD $8 $9 $10 Logic17UC Regents Spr 2010 © UCBEECS 150 - L11: Processor Pipelining How data flows after posedge32rd1RegFile32rd2WE32wd5rs15rs25ws32ALU3232opLogicAddr DataInstrMemDPCQ+0x418UC Regents Spr 2010 © UCBEECS 150 - L11: Processor Pipelining Next posedge: Update state and repeat32rd1RegFile32rd2WE32wd5rs15rs25wsDPCQ19UC Regents Spr 2010 © UCBEECS 150 - L11: Processor PipeliningObservation: Logic idle most of
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