1Fall 2002 EECS150 – Lec26-ECCPage 1EECS150 - Digital DesignLecture 26 – Error Correction Codes, Linear Feedback Shift Registers (LFSRs)Nov 21, 2002John WawrzynekFall 2002 EECS150 – Lec26-ECCPage 2Outline• Error detection using parity• Hamming code for error detection/correction• Linear Feedback Shift Registers– Theory and practice2Fall 2002 EECS150 – Lec26-ECCPage 3Error Correction Codes (ECC)• Memory systems generate errors (accidentally fliped-bits)– DRAMs store very little charge per bit– “Soft” errors occur occasionally when cells are struck by alpha particles or other environmental upsets.– Less frequently, “hard” errors can occur when chips permanently fail.• Where “perfect” memory is required– servers, spacecraft/military computers, …• Memories are protected against failures with ECCs• Extra bits are added to each data-word– extra bits are used to detect and/or correct faults in the memory system– in general, each possible data word value is mapped to a unique “code word”. A fault changes a valid code word to an invalid one -which can be detected.Fall 2002 EECS150 – Lec26-ECCPage 4Simple Error Detection Coding• Each data value, before it is written to memory is “tagged” with an extra bit to force the stored word to have even parity:• Each word, as it is read from memory is “checked” by finding its parity (including the parity bit). Parity Bitb7b6b5b4b3b2b1b0p+b7b6b5b4b3b2b1b0p+c• A non-zero parity indicates an error occurred:– two errors (on different bits) is not detected (nor any even number of errors)– odd numbers of errors are detected.3Fall 2002 EECS150 – Lec26-ECCPage 5Hamming Error Correcting Code• Use more parity bits to pinpoint bit(s) in error, so they can be corrected.• Example: Single error correction (SEC) on 4-bit data – use 3 parity bits, with 4-data bits results in 7-bit code word– 3 parity bits sufficient to identify any one of 7 code word bits– overlap the assignment of parity bits so that a single error in the 7-bit work can be corrected• Group parity bits so they correspond to subsets of the 7 bits:–p1protects bits 1,3,5,7–p2protects bits 2,3,6,7–p3protects bits 4,5,6,71 2 3 4 5 6 7p1p2d1p3 d2d3d4Bit position number001 = 110011 = 310101 = 510111 = 710010 = 210011 = 310110 = 610111 = 710100 = 410101 = 510110 = 610111 = 710p1p2p3Fall 2002 EECS150 – Lec26-ECCPage 6Hamming Code Example•Example: c = c3c2c1= 101– error in 4,5,6, or 7 (by c3=1)– error in 1,3,5, or 7 (by c1=1)– no error in 2, 3, 6, or 7 (by c2=0)• Therefore error must be in bit 5.• Note the check bits point to 5• By our clever positioning and assignment of parity bits, the check bits always address the position of the error!• c=000 indicates no error1 2 3 4 5 6 7p1p2d1p3 d2d3d4– Note: parity bits occupy power-of-two bit positions in code-word.– On writing to memory:• parity bits are assigned to force even parity over their respective groups.– On reading from memory:• check bits (c3,c2,c1) are generated by finding the parity of the group and its parity bit. If an error occurred in a group, the corresponding check bit will be 1, if no error the check bit will be 0.• check bits (c3,c2,c1) form the position of the bit in error.4Fall 2002 EECS150 – Lec26-ECCPage 7Hamming Error Correcting Code• Overhead involved in single error correction code:–let p be the total number of parity bits and d the number of data bits in a p + d bit word.– If p error correction bits are to point to the error bit (p + dcases) plus indicate that no error exists (1 case), we need:2p>= p + d + 1,thus p >= log(p + d + 1)for large d, p approaches log(d)• Adding on extra parity bit covering the entire word can provide double error detection1 2 3 4 5 6 7 8p1p2d1p3 d2d3d4 p4• On reading the C bits are computed (as usual) plus the parity over the entire word, P:C=0 P=0, no errorC!=0 P=1, correctable single errorC!=0 P=0, a double error occurredC=0 P=1, an error occurred in p4 bitTypical modern codes in DRAM memory systems:64-bit data blocks (8 bytes) with 72-bit code words (9 bytes).Fall 2002 EECS150 – Lec26-ECCPage 8Linear Feedback Shift Registers (LFSRs)• These are n-bit counters exhibiting pseudo-random behavior.• Built from simple shift-registers with a small number of xor gates.•Used for:– pseudo-random number generation– counters– error checking and correction• Advantages:– very little hardware– high speed operation• Example 4-bit LFSR:QDQ1QDQ2QDQ3QDQ4CLK5Fall 2002 EECS150 – Lec26-ECCPage 94-bit LFSR• Circuit counts through 24-1 different non-zero bit patterns.• Leftmost bit decides whether the “10011” xor pattern is used to compute the next value or if the register just shifts left.• Can build a similar circuit with any number of FFs, may need more xor gates.• In general, with n flip-flops, 2n-1different non-zero bit patterns. • (Intuitively, this is a counter that wraps around many times and in a strange way.) 0 0 0 1 0xor 0 0 0 0 0 0 0 0 1 0 0 xor 0 0 0 0 0 0 0 1 0 0 0 xor 0 0 0 0 0 0 1 0 0 0 0 xor 1 0 0 1 1 0 0 0 1 1 0 xor 0 0 0 0 0 0 0 1 1 0 0 xor 0 0 0 0 0 0 1 1 0 0 0 xor 1 0 0 1 1 0 1 0 1 1Q4 Q3 Q2 Q10001001001001000001101101100101101011010011111101111110110010001QDQ1QDQ2QDQ3QDQ4CLKFall 2002 EECS150 – Lec26-ECCPage 10Applications of LFSRs• Performance:– In general, xors are only ever 2-input and never connect in series.– Therefore the minimum clock period for these circuits is:T > T2-input-xor+ clock overhead– Very little latency, and independent of n!• This can be used as a fast counter, if the particular sequence of count values is not important. – Example: micro-code micro-pc• Can be used as a random number generator. – Sequence is a pseudo-random sequence:• numbers appear in a random sequence• repeats every 2n-1 patterns– Random numbers useful in:• computer graphics• cryptography• automatic testing• Used for error detection and correction• CRC (cyclic redundancy codes)• ethernet uses them6Fall 2002 EECS150 – Lec26-ECCPage 11Galois Fields - The theory behind LFSRs• LFSR circuits performs multiplication on a field.• A field is defined as a set with the following:– two operations defined on it:• “addition” and “multiplication”– closed under these operations – associative and
View Full Document
Unlocking...