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Time TableMotivationIntroductionPrelabLab ProcedureLab2TopBehavioral AccumulatorStructural Peak DetectorStructural RegisterStructural ComparatorStructural Peak DetectorReferencesLab 2 CheckoffEECS150: Lab 2, Designing with VerilogUC Berkeley College of EngineeringDepartment of Electrical Engineering and Computer ScienceSeptember 4, 20081 Time TableASSIGNED Friday, September 5thDUE Week 3: September 14th− 20th, 10 minutes after your lab section starts2 MotivationIn this lab you will learn how to express a circuit design in a Hardware Description Language (HDL),namely Verilog. By creating two similar designs in behavioral and structural Verilog, you will get a chanceto not only familiarize yourself with different styles of Verilog, but also with the ModelSim simulator.3 IntroductionTo support the creation of very efficient circuits, and as an effort to ease entry of old designs, andimporting designs from other environments, Verilog supports the use of universally accessible primitivegates like and, or and not. In addition, it supports dataflow and behavioral modeling, which allow thedesign of more efficient control.In this lab, you will investigate the use of the two primary kinds of Verilog: structural and behavioral.You will create two similar, simple modules. One module will be specified in behavioral Verilog, whereyou will describe the function of the circuit succinctly and rely on the modeling and synthesis CAD toolsto determine the exact circuit. The other circuit will be written in structural Verilog, were you willdescribe the circuit down to the gate level. The final piece of Verilog in this lab will be the testbench,which, though also written in behavioral Verilog, is a little different in that it cannot be synthesized.This is because it describes an artificial set of test stimulus rather than an actual circuit.4 PrelabPlease make sure to complete the prelab before you attend your lab section. You will not be able tofinish this lab in 3 hrs otherwise!1. Read this handout thoroughly. Pay particular attention to Section Section 5 as it describes indetail the circuits you must create.2. Examine the Verilog provided for this week’s lab.• Make sure you understand exactly how the Lab2Testbench works.3. Write all of your Verilog ahead of time.1• You should add more test cases to Lab2Testbench.v. You will not get checked off forthis lab without a more thorough testing of your modules.4. You will need the entire 3 hr lab to test and debug your Verilog!5 Lab ProcedureSince we expect you to write your Verilog ahead of time, and Verilog is nothing more than a bunch ofstandard text in a file with a *.v extension, you can do this part of the lab entirely from homein your favorite text editor (we recommend notepad). Or you can come into the lab and use the toolsthere. For those of you who like maintaining a single Xilinx Project Navigator project for each lab,you can even create the project ahead of time and write your Verilog from within ProjectNavigator.Whatever editor you use to create your Verilog files, at some point you will need to add all ofthe Verilog files (including Lab2Top and Lab2Testbench) to a new Xilinx Project Navigatorproject, or to a new ModelSim project, to test your code and get it checked off.Remember to manage your Verilog, projects and folders well. Doing a poor job of managingyour files can cost you hours of rewriting code, if you accidentally delete your files.5.1 Lab2TopIn this lab you will be building the two sub-modules of Lab2Top, namely an Accumulator and a PeakDetector(see Figure 1). Lab2Top takes a string of 8-bit inputs and maintains both a running sum of the inputsusing an Accumulator and the largest of the inputs using a PeakDetector. The PeakSelect input to Lab2Topcan be used to select which of these values appears at the output Out.Figure 1 Hierarchy of ModulesLab2TopStructural BehavioralAccumulatorBehavioralPeakDetectorStructuralReg8StructuralComp8 StructuralComp1StructuralFDCEPrimitiveGate PrimitivesFigure 2 shows a high-level block diagram of Lab2Top. Table 1 shows a table specifying its ports andtheir purposes and a hierarchy of the modules that you will need to build to complete this lab.2Figure 2 Lab2Top High Level Block DiagramOutSelectInLab2TopAccumulatorPeak DetectorMuxTable 1 Port Specification for Lab2TopSignal Width Dir DescriptionIn 8 I The input valueOut 8 O The output value from either the PeakDetector or AccumulatorEnable 1 I Notify Lab2Top to accept the current input at InPeakSelect 1 I Selects the output form the PeakDetector when 1’b1Clock 1 I The Clock signalReset 1 I Reset both the Accumulator and the PeakDetector5.2 Behavioral AccumulatorSee Figure 3 for a diagram of the Accumulator you are to build.Figure 3 The AccumulatorRegister+AccumulatorInEnableClockOutReset88881. In the text editor of your choice (we recommend notepad) create a file called Accumulator.v inwhich you will define a single module called Accumulator.(a) This module should have the ports listed in Table 2.(b) Be sure to use good Verilog style. You’ll be graded on this!2. Specify your module entirely in behavioral Verilog.(a) Our solution takes 4 lines of behavioral Verilog (not counting declarations).(b) You may not instantiate any other module within your accumulator.(c) You may wish to refer to the lab lecture slides for examples of behavioral Verilog.3Table 2 Port Specification for AccumulatorSignal Width Dir DescriptionIn 8 I The input value to be added to the total outputOut 8 O The sum of all previous input valuesEnable 1 I Notify the accumulator to add In to OutClock 1 I The Clock signal, the output changes only on rising edgesReset 1 I Reset the output to 8’h003. Types of Assignment= A blocking assignment is written as “=” and should be used in combinational logic.<= A non-blocking assignment is written as “<=” and should be used for sequential logic,namely anywhere you have an always @ (posedge Clock).(a) Note that these kinds of assignments refer only to always blocks. The assign keyword alwaysrequires a simple “=.”4. Reg vs. Register(a) The keyword reg in Verilog names a location into which an always block can place a value. Itdoes not create any kind of register, it is merely a poorly named artifact of days past.(b) always @ (posedge Clock) implies a register.• Any reg assigned using non-blocking assignment (<=) in an always @ (posedge Clock)block will become a register during synthesis.5. Test this module


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Berkeley COMPSCI 150 - Lab 2

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