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Berkeley COMPSCI 150 - Verilog Simulation and Mapping

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EECS150 Spring 2002 Lab 4 Verilog Simulation MappingUNIVERSITY OF CALIFORNIA AT BERKELEYCOLLEGE OF ENGINEERINGDEPARTMENT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCELab 4Verilog Simulation Mapping1 MotivationIn this lab you will learn how to use a hardware description language (verilog) to create adesign. You will explore different levels of implementation, varying the level at whichthe definition of your design is crafted structurally versus behaviorally.2 IntroductionModern day circuit design is done mainly using hardware description languages (HDLs.)Two popular HDLs are verilog and VHDL. In this class we will use verilog. Verilog canbe written using either structural or behavioral descriptions. The code can either useportable standard verilog or manufacturer specific components such as Xilinx primitives.For the purposes of this lab, we will attempt to restrict ourselves to the use of portablestandard verilog.Once written, verilog code can then be run through sophisticated CAD tools such as alogic synthesis tool that will generate the actual low-level gates. In the case of an FPGAthe verilog will create a netlist of LUTS, FFs and CLBs. In the case of an ASIC the resultmay be a netlist of transistors. A simulation can be run on the functional verilog code orafter synthesis on the generated netlist. The functional simulation verifies thefunctionality of the verilog code but does not include realistic timing information, such asgate delays. After the code is run through a logic synthesis tool the timing simulation runon the generated netlist includes timing statistics yielding more accurate results.3 Prelab & Brief Overview of Structural vs. BehavioralWARNING: You will not finish this lab during the lab section unless you do thePrelab beforehand!1. Read and understand the entire lab handout.2. Create a verilog testbench to test your designs. A skeleton testbench is provided foryou on the website (in the same place this write-up is located).3. Write the verilog for all four parts of the lab. You will need as much time in lab aspossible to debug your code.4. This lab assumes some familiarity with the tool flow presented in the previous lab. Re-reading portions of the previous lab assignment to re-familiarize yourself with the toolflow may be beneficial.Don’t expect to be able to write and debug your code during the lab session.Structural vs. Behavioral.One may consider the relation between the structural and behavioral nature of pieces of adesign as being directly linked to the point at which subcomponents cease to havesubcomponents.One can visualize the situation as follows:StructuralEach subcomponent exists atsome particular levelBehavioralIf the level of design for a component is structural, then it will be composed of one ormore sub modules, each of which exists closer to (or in) the behavioral portion of thedesign. The division of a design into structural and behavioral parts can be thought of asproportional to the degree of complexity of the behavioral components used in the design.Using this lab’s accumulator as an example, the four parts of the lab break down asfollows:Part I.Modules:Accumulator(Hierarchy view)BehavioralAccumulatorEntirely behavioral, there are no structural modules, and hence no discernable divisionbetween the two portions of the design.Part II. Modules:Structural AccumulatorModules:(Hierarchy view) Behavioral RegisterAdderAccumulatorRegister AdderPart III.Structural Modules:AccumulatorRegisterAdderBehavioral Modules:FlipFlopFull-AdderAccumulatorRegister AdderFlip Flop Full-adder CellPart IV.Structural Modules:AccumulatorRegisterAdderFull-Adder CellModules: Behavioral Flip-FlopGatesAccumulatorRegister AdderFlip Flop Full-adder CellAND XOR OR4 ProcedurePart I – Behavioral Accumulator1. In the text editor of your choice, create a new file and name it top.v. In this filecreate a module called top. Add four ports to your module:Port Name Width Direction DescriptionClk 1 Input Clock SignalRst 1 Input Reset signal for any FFsIn 16 Input The input to your designOut 16 Output The output of your design2. Using a purely behavioral specification, create your entire accumulator in thismodule.3. Using ModelSim, test the functionality of your design with your verilog test bench.4. Once you are convinced your design is functional, use Synplify to synthesize yourdesign. Open the Xilinx Design manager and proceed with the Placement andRouting stages.5. Examine the reports generated, noting the timing constraints and number of LUTsused. Open up the Floorplanner and visually examine the layout.6. Open ModelSim and use the timing constraints from the reports along with yourtestbench to verify the delay of the critical path.Part II – Structural Accumulator from a Behavioral Register and a BehavioralAdder1. Create a new verilog file called top.v with a module called top with the sameport list as Part I (put it in another directory than the one in which the first top.v wasdefined).2. Create your design using a behavioral specification for an adder and a behavioralspecification for a register, each defined as its own module. Instantiate one of eachof these, and connect them together (structurally) in your top module (in top.v).3. Do steps 4 and 5 from Part I. If the mapping report shows a difference in the numberand/or type of parts used, can these differences be noticed in your visual inspectionvia the floorplanner?4. Do step 6 from from Part IPart III – Structural Accumulator from Structural Register Composed ofBehavioral FlipFlops and a Structural Adder Composed of Behavioral Full-AdderCellsFor this part follow the same steps as in Part II, except use verilog primitives andadditional levels of hierarchy to build the adder and register. Do not use the verilog +,-,/,* functions for the adder. Create full-adder cells with boolean equations usingassign statements with &,|,ˆ, and ˜(Thus, this will be a Dataflow definition of thefull-adder cells). Connect the full-adder cells together to form a ripple adder, and connectthe FlipFlops together to form a register. The adder and register thus created should becompatible with your previous instantiations of a behavioral register and adder in yourtop module, so the top module should not require any code changes.Part IV – Structural Accumulator from Structural Register Composed ofBehavioral FlipFlops and a Structural Adder from Structural Full-Adder CellsComposed of Instances of Logic Gates.Here


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Berkeley COMPSCI 150 - Verilog Simulation and Mapping

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