EECS150 Fall 2000 Lab6 - Nasty Realities by Sammy SySectionsComponents (1)Components (2)Components (3)Components (4)Components (5)What to do in this labCapacitance vs Propagation delay (1)Capacitance vs Propagation delay (2)Reflection and Termination (1)Reflection and Termination (2)Capacitive Coupling (1)Capacitive Coupling (2)Capacitive Coupling (3)Xilinx Tips (1)Xilinx Tips (2)EECS150 Fall 2000Lab6 - Nasty Realitiesby Sammy SyDon’t let the title scare you. Even though the final project might be nasty, this lab is not.SectionsSome information on the electrical components in this labCapacitance vs Propagation delayReflection and TerminationCapacitive CouplingExtra Xilinx tipsComponents (1)BreadboardWhich holes are connected with which?Figure 1a Breadboard connectionsComponents (2)Ribbon cableIs interference a problem?We’ll find outFigure 1b Ribbon cable DIP plugComponents (3)Resistors and capacitorsTime to figure out how those colors on resistors and numbers on capacitors meanDetailed description on the lab handoutExample: red-black-brown = 200 ohm (red = 2, black = 0, brown 1)Components (4)74F04PC hex inverter chipEssentially just a bunch of inverter gatesRemember an inverter requires input, and VCC and GND.Figure 2b 74F04PC hex inverter pinoutsComponents (5)We also need a bunch of normal wires to hook them upRemind yourself how to play with the pulse generatorMore practice with the mighty oscilloscopeWhat to do in this labYou will be building several simple circuits to measure gate delays, and observe how reflection and capacitance affect electrical signals.The lab handout gives you the step-by-step procedures.Some motivations.Capacitance vs Propagation delay (1)Capacitance is evilWhy?It limits how fast a gate transition can take place.In fact, all conductors are subject to this evilness - for example, two wires together.Capacitance vs Propagation delay (2)Ring oscillatorNo stable stateTherefore, those inverters will be switching as fast as their capacitance allows.T = 2 * delay * NFigure 2a 5-stage ring oscillatorReflection and Termination (1)What’s reflection?If you view electrical signal as propagation of E&M waves, then a wire is no different than optical fiber.When the signal hits a dead end, it bounces back and interferes with itself.Can be solved by proper termination.Reflection and Termination (2)Terminate by eliminating those dead ends.Add some load (i.e.: resistance).I once heard that TV cable companies detect undesired “fanouts” by sending a strong pulse to the wire and count the number of reflections received.Now you can outsmart them.Capacitive Coupling (1)Recall the ribbon cableSignal on wire interferes with the neighboring wires. It’s especially noticeable in long and crowded wires.An undriven wire is more easily affected.Capacitive Coupling (2)For example, say we have 3 wires A, B and C arranged linearly (i.e. B is between A and B).Let A = some signalLet B = undrivenLet C = some other signalBecause B is undriven, it’s easily influenced by A and CCapacitive Coupling (3)Simultaneously, B affects A and C.We can introduce a “shield” to protect the signals in A and C.If we ground B, it becomes much less likely to be manipulated by A and C.Thus, A and C won’t step onto each others’ toes.Xilinx Tips (1)This lab doesn’t need Xilinx (relieved!)Difference between FDC and FDR (similarly applies to CC8CE vs CC8RE, etc)FDC = D-type flipflop with asynchronous clearFDR = D-type flipflop with synchronous resetXilinx Tips (2)Keep the clock signal clean!Read the implementation logOnce you’ve made something into a macro, the original schematic file is not used by the project anymore.Ground
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