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Berkeley COMPSCI 150 - Computer Organization

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CS 150 – Spring 2007 – Lec #12: Computer Org I - 1Computer Organization! Computer design as an application of digital logic designprocedures! Computer = processing unit + memory system! Processing unit = control + datapath! Control = finite state machine" Inputs = machine instruction, datapath conditions" Outputs = register transfer control signals, ALU operation codes" Instruction interpretation = instruction fetch, decode, execute! Datapath = functional units + registers" Functional units = ALU, multipliers, dividers, etc." Registers = program counter, shifters, storage registersCS 150 – Spring 2007 – Lec #12: Computer Org I - 2Tri-State Buffers! 0, 1, Z (high impedance state)inoutOEif OE then Out = In else “disconnected”+inout+outOEinBasic InverterInverting BufferCS 150 – Spring 2007 – Lec #12: Computer Org I - 3Tri-States vs. MuxSel2:1 Mux0 1A BASel0BSel1DECSel01Scales poorly for high fan-inor wide bit widthsBuffer circuits simple!Scales nicely for high fan-inand wide bit widths!CS 150 – Spring 2007 – Lec #12: Computer Org I - 4Register TransferLdCASel0BSel1DECSel01C ! A Sel ! 0; Ld ! 1C ! B Sel ! 1; Ld ! 1ClkSelLdClkA on BusLd Cfrom BusBusB on Bus?CS 150 – Spring 2007 – Lec #12: Computer Org I - 5Open Collector Concept“1”“0”+Bad! Short circuit!Low resistance path fromVdd to Gnd+ResistivePull-up“1”“0”Wired AND Configuration:If any attached device wantswire to be “0”, it winsIf all attached devices wantwire to be “1”, it isDefault is highMust activelydrive it lowCS 150 – Spring 2007 – Lec #12: Computer Org I - 6central processing unit (CPU)instruction unit– instruction fetch and interpretation FSMexecution unit– functional unitsand registersaddressread/writedataProcessorMemorySystemStructure of a Computer! Block diagram viewcontrol signalsdata conditionsData PathControlCS 150 – Spring 2007 – Lec #12: Computer Org I - 7LD asserted during a lo-to-hi clock transition loads new data into FFsOE asserted causes FF state to be connected to output pins; otherwise they are left unconnected (high impedance)OEQ7Q6Q5Q4Q3Q2Q1Q0LDD7D6D5D4D3D2D1D0CLKRegisters! Selectively loaded – EN or LD input! Output enable – OE input! Multiple registers –!group 4 or 8 in parallelCS 150 – Spring 2007 – Lec #12: Computer Org I - 8Register Transfer! Point-to-point connection" Dedicated wires" Muxes on inputs ofeach register! Common input from multiplexer" Load enablesfor each register" Control signalsfor multiplexer! Common bus with output enables" Output enables and loadenables for each registerrtMUXrsMUXrdMUXR4MUXrsMUXrt rd R4BUSrs rt rd R4CS 150 – Spring 2007 – Lec #12: Computer Org I - 9RERBRAWEWBWAD3D2D1D0Q3Q2Q1Q0Register Files! Collections of registers in one package" Two-dimensional array of FFs" Address used as index to a particular word" Separate read and write addresses so can do both at same time! 4 by 4 register file" 16 D-FFs" Organized as four words of four bits each" Write-enable (load)" Read-enable (output enable)CS 150 – Spring 2007 – Lec #12: Computer Org I - 10RDWRA9A8A7A6A5A4A3A2A2A1A0IO3IO2IO1IO0Memories! Larger Collections of Storage Elements" Implemented not as FFs but as much more efficient latches" High-density memories use 1-5 switches (transitors) per bit! Static RAM – 1024 words each 4 bits wide" Once written, memory holds forever (not true for denser dynamicRAM)" Address lines to select word (10 lines for 1024 words)" Read enable# Same as output enable# Often called chip select# Permits connection of manychips into larger array" Write enable (same as load enable)" Bi-directional data lines# output when reading, input when writingCS 150 – Spring 2007 – Lec #12: Computer Org I - 11Instruction Sequencing! Example – an instruction to add the contents of two registers(Rx and Ry) and place result in a third register (Rz)! Step 1: Get the ADD instruction from memory into an instructionregister! Step 2: Decode instruction" Instruction in IR has the code of an ADD instruction" Register indices used to generate output enables for registers Rxand Ry" Register index used to generate load signal for register Rz! Step 3: Execute instruction" Enable Rx and Ry output and direct to ALU" Setup ALU to perform ADD operation" Direct result to Rz so that it can be loaded into registerCS 150 – Spring 2007 – Lec #12: Computer Org I - 12Instruction Types! Data Manipulation" Add, subtract" Increment, decrement" Multiply" Shift, rotate" Immediate operands! Data Staging" Load/store data to/from memory" Register-to-register move! Control" Conditional/unconditional branches in program flow" Subroutine call and returnCS 150 – Spring 2007 – Lec #12: Computer Org I - 13Elements of the Control Unit (akaInstruction Unit)! Standard FSM Elements" State register" Next-state logic" Output logic (datapath/control signaling)" Moore or synchronous Mealy machine to avoid loops unbroken by FF! Plus Additional ”Control" Registers" Instruction register (IR)" Program counter (PC)! Inputs/Outputs" Outputs control elements of data path" Inputs from data path used to alter flow of program (test if zero)CS 150 – Spring 2007 – Lec #12: Computer Org I - 14! Control State Diagram (for each diagram)" Reset" Fetch instruction" Decode" Execute! Instructions partitionedinto three classes" Branch" Load/store" Register-to-register! Different sequencethrough diagram foreach instruction typeResetInitializeMachineRegister-to-RegisterBranchNot TakenBranch TakenInstruction ExecutionInitFetchInstr.XEQInstr.Load/StoreBranchIncr.PCCS 150 – Spring 2007 – Lec #12: Computer Org I - 15CinAinBinSumCoutFAHAAinBinSumCinCoutHAData Path (Hierarchy)! Arithmetic circuits constructed in hierarchical anditerative fashion" Each bit in datapath isfunctionally identical" 4-bit, 8-bit, 16-bit,32-bit datapathsCS 150 – Spring 2007 – Lec #12: Computer Org I - 161616A BS ZNOperation16Data Path (ALU)! ALU Block Diagram" Input: data and operation to perform" Output: result of operation and status informationCS 150 – Spring 2007 – Lec #12: Computer Org I - 1716ZNOP16ACREG1616Data Path (ALU + Registers)! Accumulator" Special register" One of the inputs to ALU" Output of ALU stored back in accumulator! One-address instructions" Operation and address of one operand" Other operand and destinationis accumulator register" AC <– AC op Mem[addr]" ”Single address instructions”(AC implicit operand)! Multiple


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Berkeley COMPSCI 150 - Computer Organization

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