1Spring 2002 EECS150 - Lec05-FPGAPage 1EECS150 -Digital DesignLecture 5 - Field Programmable Gate Arrays (FPGAs)February 4, 2002John WawrzynekSpring 2002 EECS150 - Lec05-FPGAPage 2Outline• What are FPGAs?• Why use FPGAs (a short history lesson).• FPGA variations• Internal logic blocks.• Break/Announcements• Designing with FPGAs.• Specifics of Xilinx 4000 series.Spring 2002 EECS150 - Lec05-FPGAPage 3FPGA Overview• Basic idea: two-dimensional array of logic blocks and flip-flops with a means for the user to configure:1. the interconnection between the logic blocks,2. the function of each block.Simplified version of FPGA internal architecture:Spring 2002 EECS150 - Lec05-FPGAPage 4Why FPGAs?• By the early 1980’s most of the logic circuits in typical systems where absorbed by a handful of standard large scale integrated circuits (LSI). – Microprocessors, bus/IO controllers, system timers, ...• Every system still had the need for random “glue logic” to help connect the large ICs:– generating global control signals (for resets etc.)– data formatting (serial to parallel, multiplexing,etc.) • Systems had a few LSI components and lots of small low density SSI (small scale IC) and MSI (medium scale IC) components.Spring 2002 EECS150 - Lec05-FPGAPage 5Why FPGAs?• Custom ICs where sometimes designed to replace the large amount of glue logic:– reduced system complexity and manufacturing cost, improved performance.– However, custom ICs are relatively very expensive to develop, and delay introduction of product to market (time to market) because of increased design time. • Note: need to worry about two kinds of costs:1. cost of development, sometimes called non-recurring engineering (NRE)2. cost of manufacture– A tradeoff usually exists between NRE cost and manufacturing coststotalcostsnumber of units manufactured (volume)NREABSpring 2002 EECS150 - Lec05-FPGAPage 6Why FPGAs?• Therefore the custom IC approach was only viable for products with very high volume (where NRE could be amortized), and which were not TTM sensitive.• FPGAs were introduced as an alternative to custom ICs for implementing glue logic:– improved density relative to discrete SSI/MSI components (withinaround 10x of custom ICs)– with the aid of computer aided design (CAD) tools circuits could be implemented in a short amount of time (no physical layout process, no mask making, no IC manufacturing)• lowers NREs• shortens TTM• Because of Moore’s law the density (gates/area) of FPGAs continued to grow through the 80’s and 90’s to the point where major data processing functions can be implemented on a single FPGA.2Spring 2002 EECS150 - Lec05-FPGAPage 7Why FPGAs?• FPGAs continue to compete with custom ICs for special processingfunctions (and glue logic) but now also compete with microprocessors in dedicated and embedded applications.– Performance advantage over microprocessors because circuits can be customized for the task at hand. Microprocessors must provide special functions in software (many cycles).• Summary:ASIC = custom IC, MICRO = microprocessorperformance NREsUnitcost TTMASIC ASIC ASICFPGAMICROFPGAMICROFPGAMICROFPGAASICMICROSpring 2002 EECS150 - Lec05-FPGAPage 8FPGA Variations• Families of FPGA’s differ in:– physical means of implementing user programmability,– arrangement of interconnection wires, and– the basic functionality of the logic blocks.• Most significant difference is in the method for providing flexible blocks and connections: • Anti-fuse based (ex: Actel)+ Non-volatile, relatively small– fixed (non-reprogrammable)Spring 2002 EECS150 - Lec05-FPGAPage 9User Programmability• Latches are used to:1. make or break cross-point connections in the interconnect2. define the function of the logic blocks3. set user options:• within the logic blocks• in the input/output blocks• global reset/clock• “Configuration bit stream” can be loaded under user control:– All latches are strung together in a shift chain:• Latch-based (Xilinx, Altera, …)+ reconfigurable– volatile– relatively large.latchSpring 2002 EECS150 - Lec05-FPGAPage 10Idealized FPGA Logic Block• 4-input look up table (LUT)– implements combinational logic functions• Register– optionally stores output of LUT4-LUT FF10latchLogic Blockset by configuration bit-stream4-input "look up table"OUTPUTINPUTSSpring 2002 EECS150 - Lec05-FPGAPage 114-LUT Implementation• n-bit LUT is implemented as a 2nx 1 memory:– inputs choose one of 2n memory locations.– memory locations (latches) are normally loaded with values from user’s configuration bit stream.– Inputs to mux control are the CLB inputs.• Result is a general purpose “logic gate”. – n-LUT can implement anyfunction of n inputs!latchlatchlatchlatch16 x 1mux16INPUTSOUTPUTLatches programmed as partof configuration bit-streamSpring 2002 EECS150 - Lec05-FPGAPage 12LUT as general logic gate• An n-lut as a direct implementation of a function truth-table.• Each latch location holds the value of the function corresponding to one input combination.0000 F(0,0,0,0)0001 F(0,0,0,1)0010 F(0,0,1,0)0011 F(0,0,1,1)0011010001010110011110001001101010111100110111101111INPUTSstore in 1st latchstore in 2nd latchExample: 4-lutExample: 2-lutORANDINPUTS11 1 110 0 101 0 100 0 0Implements any function of 2 inputs. How many of these are there?How many functions of n inputs?3Spring 2002 EECS150 - Lec05-FPGAPage 13Announcements• Quiz results• Administrative Q&A.• New reading posted:– large section of Xilinx 4000 databook– All of chapter 2 in ManoSpring 2002 EECS150 - Lec05-FPGAPage 14FPGA Generic Design Flow• Design Entry:– Create your design files using:• schematic editor or • hardware description language (Verilog, VHDL)• Design “implementation” on FPGA:– Partition, place, and route to create bit-stream file• Design verification:– Use Simulator to check function,– other software determines max clock frequency.– Load onto FPGA device (cable connects PC to development board)• check operation at full speed in real environment.Spring 2002 EECS150 - Lec05-FPGAPage 15Example Partition, Placement, and Route• Example Circuit:– collection of gates and flip-flops• Idealized FPGA structure:Circuit combinational logic must be “covered” by 4-input 1-output “gates”.Flip-flops from circuit must map to FPGA flip-flops. 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