EECS 150 Components Design Techniques For Digital Systems Lecture 28 Graphics Processors 2009 4 30 John Lazzaro www cs berkeley edu lazzaro Play TAs CS 194 6 alums Chris Ilia and Chen www inst eecs berkeley edu cs150 EECS 150 L28 Graphics Processors UC Regents Spring 2009 UCB 1 Today Graphics Processors Computer Graphics A brief introduction to the pipeline Stream Processing Casting the graphics pipeline into hardware Unified Pipelines GeForce 8800 from Nvidia introduced in 2006 Larrabee Intel multi core graphics architecture SIGGRAPH 2008 EECS 150 L28 Graphics Processors UC Regents Spring 2009 UCB 2 Personal computer graphics architecture Case Study Mac Mini PowerPC edition EECS 150 L28 Graphics Processors UC Regents Spring 2009 UCB 3 Personal computer graphics architecture EECS 150 L28 Graphics Processors UC Regents Spring 2009 UCB 4 C H A P T E R 2 Architecture Mac Mini G4 System block diagram Figure 2 1 Block diagram CPU PowerPC G4 Freescale PowerPC G4 microprocessor L2 cache 512K 1 1 Processor bus How the CPU talks to everything else 167 MHz MaxBus DDR SDRAM DIMM slot Bus controller Low cost Mac Mini only has 1 Most PCs have two fast North Bridge slow South Bridge 167 MHz Memory bus Hard disk Device 0 Ultra drive ATA 100 bus Optical drive AGP 4X bus Radeon 9200 graphics IC DVI VGA composite S video output port 32 MB DDR RAM Intrepid memory controller and I O device controller Device 1 I2S FireWire PHY FireWire 400 port Ethernet PHY Ethernet port 10 100 Mbps Audio codec Headphone audio line out jack Built in speaker AirPort Extreme PCI bus Boot ROM I2C PMU power controller PCI USB 2 0 controller Power button Bluetooth USB 2 0 port 480 Mbps USB 2 0 port 480 Mbps Fan 12 Mbps USB EECS 150 L28 Graphics Processors I2S Data pump and DAA Modem module Modem port UC Regents Spring 2009 UCB 5 Main ICs and Buses C H A P T E R 2 Architecture The bus controller talks to everything else Figure 2 1 Block diagram AGP 4X bus Graphics chip PCI bus Boot ROM USB 2 PowerPC G4 microprocessor L2 cache 512K 1 1 167 MHz MaxBus ATA 100 bus For hard disk DVD CD ROM DDR SDRAM DIMM slot PCI ATA AGP devices can be bus master for Direct Memory Access DMA Disk can write RAM directly 167 MHz Memory bus Hard disk Device 0 Ultra drive ATA 100 bus Optical drive AGP 4X bus Radeon 9200 graphics IC DVI VGA composite S video output port 32 MB DDR RAM Intrepid memory controller and I O device controller Device 1 I2S FireWire PHY FireWire 400 port Ethernet PHY Ethernet port 10 100 Mbps Audio codec Headphone audio line out jack Built in speaker AirPort Extreme PCI bus Boot ROM I2C PMU power controller PCI USB 2 0 controller Power button Bluetooth USB 2 0 port 480 Mbps USB 2 0 port 480 Mbps Fan 12 Mbps USB EECS 150 L28 Graphics Processors I2S Data pump and DAA Modem module Modem port UC Regents Spring 2009 UCB 6 Main ICs and Buses C H A P T E R 2 Mac Mini Graphics sub system Architecture AGP 4X Block Hi Speed Graphics Bus diagram Figure 2 1 Dedicated Graphics RAM DDR SDRAM DIMM slot PowerPC G4 microprocessor L2 cache 512K 1 1 167 MHz MaxBus AGP 4X bus 167 MHz Memory bus Radeon 9200 graphics IC 32 MB DDR RAM ATI Radeon 9200 Graphics Processing Unit GPU DVI VGA composite S video output port To Display FireWire PHY FireWire 400 port Ethernet PHY Ethernet port 10 100 Mbps Hard disk Device 0 Ultra drive ATA 100 bus Intrepid memory controller EECS 150 L28 Graphics Processors and I O device controller Optical drive Device 1 I2S Audio Headphone audio Average selling price ASP for GPUs 30line out jack codec Built in speaker UC Regents Spring 2009 UCB 7 AirPort Extreme PCI bus EECS 150 L28 Graphics Processors UC Regents Spring 2009 UCB 8 EECS 150 L28 Graphics Processors UC Regents Spring 2009 UCB 9 GPU cost a significant part of total Bill of Materials Parts cost in volume 274 69 Parts manufacturing cost 283 37 Source iSuppli corporation 10 2560 A b o u t 12 M B f ra m e 24 bi t 24 f ra m pi xe ls e s se c 3 00 M B s ec ond EECS 150 L28 Graphics Processors 1 6 0 0 UC Regents Spring 2009 UCB 11 Anatomy of a dumb graphics card H A P T E R hitecture ure 2 1 AGP 4X 1 1 GB s Can handle 24 f s 300 MB s for a Block diagram 2560x1600 display P T E R ure 2 2 12 MB Frame Buffer PowerPC G4 microprocessor L2 cache 512K 1 1 167 MHz MaxBus 12 MB Frame Buffer Double Buffering CPU writes next frame in one buffer Control DVI VGA composite S video 1 Block diagram logic sends output port DDR SDRAM Control Logic 167 MHz this DIMM slot Memory 32 MB PowerPCCPU G4 Problem has bus frame DDR RAM microprocessor L2 cache 512K a 1 1 new to compute DVI Formatter D A out of FireWire FireWire 400 port pixel 10 ns 167every MHz PHY other MaxBus AGP 4X 10 clock cycles for Radeon Ethernet Ethernet port bus buffer to DVI VGA composite S video 9200 PHY 10 100 Mbps a 1 GHz CPU clock graphics IC output port display DRAM Device 0 Hard disk M slot drive AGP 4X bus Radeon 9200 graphics IC EECS 150 L28 Graphics Processors 167 MHz Intrepid Ultra Memory I2S memory 32 MBAudio ATA 100 bus bus controller DDR RAM codec and I O Built in device UC Regents Spring 2009 UCB Headphone audio line out jack 12 Q What kind of graphics are we accelerating A In 2009 interactive entertainment 3 D games In the 1990s 2 D acceleration fast windowing systems games like Pac Man Graphics Acceleration Q In a multi core world why should we use a special processor for graphics A Programmers generally use a certain coding style for graphics We can design a processor to fit the style Next An intro to 3 D graphics EECS 150 L28 Graphics Processors UC Regents Spring 2009 UCB 13 The Triangle Simplest closed shape that may be defined by straight edges With enough triangles you can make anything EECS 150 L28 Graphics Processors UC Regents Spring 2009 UCB 14 A cube whose faces are made up of triangles This is a 3 D model of a cube model includes faces we can t see in this view A sphere whose faces are made up of triangles With enough triangles the curvature of the sphere can be made arbitrarily smooth EECS 150 L28 Graphics Processors UC Regents Spring 2009 UCB 15 A teapot famous object in computer graphics history A wire frame of triangles can capture the 3 D shape of complex man made objects EECS 150 L28 Graphics Processors UC Regents Spring 2009 UCB 16 Triangle defined by 3 vertices By transforming v f v all vertices in a 3 D …
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