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Berkeley COMPSCI 150 - Lec 14 - Timing

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EECS 150 Components and Design Techniques for Digital Systems Lec 14 Timing David Culler Electrical Engineering and Computer Sciences University of California Berkeley http www eecs berkeley edu culler http www inst eecs berkeley edu cs150 1 Outline General Model of Synchronous Systems Performance Limits Delay in logic gates Delay in wires Delay in combinational networks Clock Skew Delay in flip flops Glitches 2 General Model of Synchronous Circuit c lo c k in p u t in p u t CL re g CL re g o u tp u t o p t io n f e e d b a c k o u tp u t All wires except clock may be multiple bits wide Registers reg collections of flip flops clock distributed to all flip flops typical rate Combinational Logic Blocks CL no internal state output only a function of inputs Particular inputs outputs are optional Optional Feedback 3 Example Circuit Parallel to Serial Converter All signal paths single bit wide Registers are single flip flops Combinational Logic blocks are simple multiplexors No feedback in this case 4 General Model of Synchronous Circuit c lo c k in p u t in p u t CL re g CL re g o u tp u t o p t io n f e e d b a c k o u tp u t How do we measure performance operations sec cycles sec What limits the clock rate What happens as we increase the clock rate 5 Limitations on Clock Rate 1 Logic Gate Delay What are typical delay values 2 Delays in flip flops in p u t D o u tp u t c lk t Q s e tu p t im e c lo c k to Q d e la y Both times contribute to limiting the clock period What must happen in one clock cycle for correct operation Assuming perfect clock distribution all flip flops see the clock at the same time All signals must be ready and setup before rising edge of clock 6 Example Parallel Serial Converter clk a b T time clk Q time mux time setup T clk Q mux setup 7 General Model of Synchronous Circuit c lo c k in p u t in p u t CL re g CL re g o u tp u t o p tio n fe e d b a c k o u tp u t In general for correct operation for all paths T time clk Q time CL time setup How do we enumerate all paths T clk Q CL setup Any circuit input or register output to any register input or circuit output setup time for circuit outputs depends on what it connects to clk Q time for circuit inputs depends on from where it comes 8 Recall L2 Transistor level Logic Circuits Inverter NOT gate Vdd Gnd what is the Vdd relationship between in and out in 0 volts out Gnd 3 volts 9 Qualitative Analysis of Logic Delay Improved Transistor Model We refer to transistor strength as the amount of current that flows for a given Vds and Vgs The strength is linearly proportional to the ratio of W L Physical property Turn it on harder allows more current to flow nFET pFET What is the effective resistance 10 Gate Switching Behavior s g Inverter d s NAND gate When does it start How quickly does it switch 11 Clarify your understanding What is the 0 1 and 1 0 behavior of a NOR gate Why do we need pMOS and nMOS devices in a pass gate used for tristate 12 Delays in a series of gates Cascaded gates Vout V in 13 Gate Delay due to fan out Fan out 2 The delay of a gate is proportional to its output capacitance Because gates 2 and 3 turn on off at a later time It takes longer for the output of gate 1 to reach the switching threshold of gates 2 and 3 as we add more output capacitance 1 3 14 Gate Delay with a general circuit Fan in Does it affect the delay of the individual gate When does the gate begin its transition What is the delay in this circuit Critical Path the path with the maximum delay from any input to any output In general we include register set up and clk to Q times in critical path calculation Why do we care about the critical path 15 What is the delay through arbitrary combinational logic 16 Announcements Lab4 5 3 5 0 7 1 5 H1 5 3 8 0 8 1 2 H2 3 3 5 0 5 0 5 E1 5 4 0 0 9 1 0 E2 3 4 6 0 7 1 6 clarity Lab3 5 3 1 0 9 1 9 length Lab2 3 4 1 0 7 1 1 content Lab1 3 3 7 0 6 0 7 workload L6 5 3 4 0 9 1 6 value understanding L5 5 3 0 0 9 2 0 clarity L4 3 2 9 2 5 0 1 workload L3 3 3 2 0 6 0 2 pace example L2 3 3 1 0 7 0 1 essential detail L1 3 3 4 0 6 0 4 clarity lecture pace ideal average stdev diff class pace Reading Katz 3 5 6 156 23 Results of class survey E3 5 3 4 0 9 1 6 17 Delay in Flip flops Setup time results from delay through first latch D clk c lk clk Q clk clk s e tu p tim e c l o c k t o Q d e l a y Clock to Q delay results from delay through second latch clk clk clk clk 18 Wire Delay In general wire behave as transmission lines signal wave front moves close to the speed of light 1ft ns Time from source to destination is called the transit time In ICs most wires are short and the transit times are relatively short compared to the clock period and can be ignored Not so on PC boards t Or long wires on fast chips Busses Global Control signals Clock x 19 Architectural Level Delay Data busses Controller datapath clock 20 Wire Delay Even in those cases where the transmission line effect is negligible Wires posses distributed resistance and capacitance v1 v2 v3 v4 Typically around half of C of gate load is in the wires Time constant associated with distributed RC is proportional to the square of the wire length v1 v2 v3 For short wires on ICs resistance is insignificant relative to effective R of transistors but C is important v4 For long wires on ICs busses clock lines global control signal etc Resistance is significant therefore distributed RC effect dominates signals are typically rebuffered to reduce delay time 21 Modern rule of thumb Transistors are cheap And their local wires Wire is what counts Often pays to do extra local computation gates to reduce wire delay 22 Clock Skew Unequal delay in distribution of the clock signal to various parts of a circuit if not accounted for …


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Berkeley COMPSCI 150 - Lec 14 - Timing

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