Spring 2002 EECS150 - Lec0-intro Page 1EECS150 - Digital DesignLecture 25 - High-level Design andOptimization 3, CPU Core ExampleApril 25, 2002Corrected Version 5/3John WawrzynekPresented by Norm ZhouSpring 2002 EECS150 - Lec0-intro Page 2Simple CPU-core Example• Why study CPU cores?1. Another large design example.2. More experience with RTL descriptions.3. A classic controller + Data-path type design example.4. Novel controller implementation: micro-programming.5. Complements prior knowledge from CS61c of MIPS processor.• This example:– Simple “8-bit” processor core with 7 instructions.– Just look at CPU-core, no memory or I/O design.– Made up just for EECS150 (pin the blame on Wawrzynek)– Sufficiently simple so all details can be covered in class.– But, general enough to be useful for real programming. Could writeand run real programs (assembly only) on it.Spring 2002 EECS150 - Lec0-intro Page 3Lecture Outline1. ISA description.2. Implementation constraints and assumptions.3. Draft micro-architecture.4. RTL for each instruction.5. Data-path refinement for each instruction.6. Specification of control signals.7. High-level controller design.8. Controller implementation.9. Micro-programming.Spring 2002 EECS150 - Lec0-intro Page 4Instruction Set Architecture (ISA)• Interfaces:• Registers:– 4 8-bit general purpose registers(GPR).– R0 reads as all 0s.– Program counter (PC) points to nextinstruction in memory. Resets to 0.• Instructions: Two formatsr-formato-format– ra, rb, rc are 2-bit GPR specifiers– r-format opcode is specified by op1– o-format opcode is specified byop1 and op2.The ISA is the abstraction that the hardware supports and providesto the software. It comprises a description of all the software visableregisters, all the instructions, and the core interfaces.CLK RSTDINDOUTAddrCPUMemoryInterface888PCR1R2R3R0op1 rc ra rbop1 rc ra op2 offset8 bits8 bits 8 bitsSpring 2002 EECS150 - Lec0-intro Page 5Instruction Set Architecture (ISA)Instruction Assembly Language Operation op1 op2add add rc,ra,rb rc←ra+rb 00 -subtract sub rc,ra,rb rc←ra-rb 01 -bit-wise nor add rc,ra,rb rc←ra NOR rb 10 -load byte ldb rc,ra,offset rc←memory[ra+offset] 11 00store byte stb rc,ra,offset memory[ra+offset]←rc 11 01branch equal beq rc,ra,offset IF rc=ra pc←pc+1+offset 11 10reserved for future use 11 11Spring 2002 EECS150 - Lec0-intro Page 6Implementation Constraints and Assumptions• Non-pipelined instruction execution.– Keeps things simple.– Take cs152 for details on processor pipelining.• Multiple cycles per instruction.– Instructions will execute one at a time over several cycles.– Within the cycles used to execute each instruction, the nextinstruction will be fetched from memory.– The final step of each instruction execution will involve a transfer ofcontrol to the next instruction.• Critical path is assumed to be both memory & ALU– therefore need complete cycle for ALU operations, and completecycle for memory read or write operation.Spring 2002 EECS150 - Lec0-intro Page 7Draft Micro-architecture• To hold the 2 bytes of currentinstruction:• Memory address register:– on memory write, address must bestable in MAR on posedge CLK– assume asynchronous read.– Will use other µarchitectureregisters as memory data-in anddata-out registers.• ALU input and output registers:– Zero output is asserted if resultof subtraction is zero.– Assume controller suppliesinput to define function of ALU.At this point, based on our assumptions we know that our data-path will need registers in addition to the ISA registers:INST2INST1MARX1 X2YALUzeroALUcontrolSpring 2002 EECS150 - Lec0-intro Page 8Instruction RTL Descriptionadd: X1←←GPR[ra];X2←←GPR[rb], RC←←INST1[5,4];Y←←X1+X2, INST1←←MEM[], PC←←PC+1, MAR←←PC+1;GPR[rc]←←Y, <dispatch>;Assumptions: Both MAR and PC are left at the end of each instruction pointing to the byte after the current instruction. <dispatch> expands as follows:switch (op1): { case 00: goto add; case 01: goto sub; case 10: goto nor; case 11:switch (op2) { case 00: goto ldb; case 01: goto stb; case 10: goto beq; } }Spring 2002 EECS150 - Lec0-intro Page 9Instruction RTL Descriptionsub: X1←←GPR[ra];X2←←GPR[rb], RC←←INST1[5,4];Y←←X1-X2, INST1←←MEM[], PC←←PC+1, MAR←←PC+1;GPR[rc]←←Y, <dispatch>;nor: X1←←GPR[ra];X2←←GPR[rb], RC←←INST1[5,4];Y←←X1 NOR X2, INST1←←MEM[], PC←←PC+1, MAR←←PC+1;GPR[rc]←←Y, <dispatch>;ldb: X1←←GPR[ra], INST2←←MEM[];X2←←INST2, RC←←INST1[5,4];MAR←←X1+X2;Y←←MEM[], PC←←PC+1, MAR←←PC+1;INST1←←MEM[], PC←←PC+1, MAR←←PC+1;GPR[rc]←←Y, <dispatch>;Spring 2002 EECS150 - Lec0-intro Page 10Instruction RTL Descriptionstb: X1←←GPR[ra], INST2←←MEM[];X2←←INST2;MAR←←X1+X2, X2←←GPR[rc]; MEM[]←←X2, PC←←PC+1, MAR←←PC+1; INST1←←MEM[],PC←←PC+1, MAR←←PC+1;<dispatch>;beq: X1←←GPR[ra], INST2←←MEM[];X2←←GPR[rb];ZERO←←X1-X2, X1←←PC, X2←←INST2;if ZERO PC←←X1+X2;PC←←PC+1, MAR←←PC+1;INST1←←MEM[],PC←←PC+1, MAR←←PC+1;<dispatch>;Spring 2002 EECS150 - Lec0-intro Page 11Data-path for add,sub,norX1 X2ALUX1Enb X2EnbALUcntl[1:0]YYEnbGPRregRWINST1regSel[1:0]000110op1op2MAR+1PC PCEnbMAREnbmemRWI1EnbControl signals shown in courier font.RCRCEnbSpring 2002 EECS150 - Lec0-intro Page 12Data-path with modifications for ldbX1 X2ALUX1EnbX2EnbALUcntl[1:0]YYEnbGPRregRWINST1regSel[1:0]000110op1op2MAR+1PCPCEnbMAREnbmemRWI1EnbINST2X2Sel0 1MARSel1 0YSel0 1RCRCEnbSpring 2002 EECS150 - Lec0-intro Page 13Data-path with modifications for stbX1 X2ALUX1EnbX2EnbALUcntl[1:0]YYEnbGPRregRWINST1regSel[1:0]000110op1op2MAR+1PCPCEnbMAREnbmemRWMEMI1EnbINST2X2Sel0 1MARSel1 0YSel0 1RCRCEnbSpring 2002 EECS150 - Lec0-intro Page 14Complete Data-path (including beq)X1 X2ALUX1EnbX2EnbALUcntl[1:0]YYEnbGPRregRWINST1regSel[1:0]000110op1op2MARPCPCEnbMAREnbmemRWMEMI1EnbINST2X2Sel0 1MARSel1 0YSel0 11 0X1Selfrom PC+1branch0 1zerofrom zeroRCRCEnbSpring 2002 EECS150 - Lec0-intro Page 15Control SignalsFrom data-path to controller:op1, op2 instruction opcode, used for dispatchNote that “zero” signal is used internal to the data-path and doesnot need to go to the controller.From controller to data-path:regRW selects
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