EECS 150 - Components and Design Techniques for Digital SystemsLec 22 – Sequential Logic - AdvancedDavid CullerElectrical Engineering and Computer SciencesUniversity of California, Berkeleyhttp://www.eecs.berkeley.edu/~cullerhttp://inst.eecs.berkeley.edu/~cs150Traversing Digital Design EE 40CS61CEECS150 wks 1-6EECS150 wks 6 - 15Sequential Circuit Design and TimingRTL & ISA Types of Latches• We have focused on D-flips– D latch => D FlipFlop => Registers (ld, clr)– Most commonly used today (CMOS, FPGA)• Many other types of latches– RS, JK, T– Should be familiar with these too• Opportunity to look much more closely at timing behavior• Latch vs Flip Flops• Timing MethodologyRecall: Forms of Sequential Logic• Asynchronous sequential logic – “state” changes occur whenever state inputs change (elements may be simple wires or delay elements)• Synchronous sequential logic – state changes occur in lock step across all storage elements (using a periodic waveform - the clock)ClockExample – ring oscillatorA B C D E X A (=X) B C D EPeriod of Repeating Waveform ( tp)Gate Delay ( td)010101(b) Timing waveformRecall: General Model of Synchronous Circuit• Our methodology so far: – registers as D flipflops with common control– Single-phase clock, edge triggered design• Assumptions underlying the clean abstraction– Input to FF valid a setup time before clock edge– Outputs don’t change too quickly after clock edge (hold time)» Clk-to-Q => hold timereg regCL CLclock inputoutputoption feedbackinputoutputinputclockTsuThX1X2•••XnswitchingnetworkZ1Z2•••ZnCircuits with Feedback• How to control feedback?– What stops values from cycling around endlessly"remember""load""data""stored value""0""1""stored value"Simplest Circuits with Feedback• Two inverters form a static memory cell– Will hold value as long as it has power applied• How to get a new value into the memory cell?– Selectively break feedback path– Load new value into cellLatches• Level-sensitive latch– holds value when clock is low– Transparent when clock is high• What does it take to build a consistent timing methodology with only latches?– Very hard! All stages transparent at same time.– Require that minimum propagation delay is greater than high phase of the clock (duty period)DQDQDQainclkbabperiodduty cycle (in this case, 50%)Clocks• Used to keep time– Wait long enough for inputs (R' and S') to settle– Then allow to have effect on value stored• Clocks are regular periodic signals– Period (time between ticks)– Duty-cycle (time clock is high between ticks - expressed as % of period)Two-phase non-overlapping clocks• Sequential elements partition into two classes• phase0 ele’ts feed phase1 • phase1 ele’ts feed phase0• Approximate single phase: each register replaced by a pair of latches on two phases• Can push logic across (retiming)• Can always slow down the clocks to meet all timing constraints DQDQainclk0babclk-0clk1c/lclk1Master-Slave Structure• Construct D flipflop from two D latchesDclkQsetup time clock to Q delayclkclk’clkclkclk’clk’clkclk’Latches vs FlipFlips• Level sensitive vs edge triggered• Very different design methodologies for correct use• Both are clocked, but latch is asynchronous– Output can change while clock is highD ClkQ Q FF Latch RSQQ'RSQR'S'QQQ'S'R'Asynchronous R-S Latch• Cross-coupled NOR gates– Similar to inverter pair, with capability to force output to 0 (reset=1) or 1 (set=1)• Cross-coupled NAND gates– Similar to inverter pair, with capability to force output to 0 (reset=0) or 1 (set=0)0101State Behavior of R-S latch• Transition Table• Sequential (output depends on history when inputs R=0, S=0) but asynchronousRSQQ'S(t) R(t) Q(t) Q(t+Δ)000 0001 1010 0011 0100 1101 1110 X111 Xholdresetsetnot allowedcharacteristic equationQ(t+Δ) = S + R’ Q(t)0010X1X1Q(t)RSTheoretical R-S Latch Behavior• State Diagram– States: possible values– Transitions: changesbased on inputsQ Q'0 1Q Q'1 0Q Q'0 0Q Q'1 1SR=00SR=11SR=00SR=10SR=01SR=00SR=10SR=00SR=01SR=11 SR=11SR=10SR=01 SR=01 SR=10SR=11possible oscillationbetween states 00 and 11RSQQ'ResetHoldSet SetResetRaceRSQ\Q100Timing BehaviorRSQQ'Observed R-S Latch Behavior• Very difficult to observe R-S latch in the 1-1 state– One of R or S usually changes first• Ambiguously returns to state 0-1 or 1-0– A so-called "race condition"– Or non-deterministic transitionSR=00SR=00 Q Q'0 1Q Q'1 0Q Q'0 0SR=10SR=01SR=00SR=10SR=00SR=01SR=11 SR=11SR=01 SR=10SR=11RSQQ'Q(t+Δ)RSQ(t)S R Q(t) Q(t+Δ)000 0001 1010 0011 0100 1101 1110 X111 Xholdresetsetnot allowedcharacteristic equationQ(t+Δ) = S + R’ Q(t)R-S Latch Analysis• Break feedback path0010X1X1Q(t)RSenable'S'Q'QR'RSGated R-S Latch• Control when R and S inputs matter– Otherwise, the slightest glitch on R or S while enable is low could cause change in value stored– Ensure R & S stable before utilized (to avoid transient R=1, S=1)SetResetS'R'enable'QQ'100clockR' and S'changing stablechanging stablestableTowards a Synchronous Design• Controlling an R-S latch with a clock– Can't let R and S change while clock is active (allowing R and Sto pass)– Only have half of clock period for signal changes to propagate– Signals must be stable for the other half of clock periodclock'S'Q'QR'RSclockRSQQ' RSQQ'RSCascading Latches• Connect output of one latch to input of another• How to stop changes from racing through chain?– Need to control flow of data from one latch to the next– Advance from one latch per clock period– Worry about logic between latches (arrows) that is too fast» Shortest paths, not critical pathsAnnouncements• Guest Lecture, Nov 29, Dr. Robert Iannucci, CTO Nokia• Sarah Lecture on Testing Methodology Thurs.• HW out tonight, due before Break• Lab lecture covers “final point”• Wireless CP this week• Next week TAs will do extended office hours M-W rather than formal lab.• Final Check off week 14• No Class Dec 6.• Final report Friday Dec. 7. Sign up for 10 min slots – 5 min presentation, 5 min Q&A– Arrive 20 mins before scheduled slot to set upMaster-Slave Structure• Break flow by alternating clocks (like an air-lock)– Use positive clock to latch inputs into one R-S latch– Use negative clock to change outputs with another R-S latch• View pair as one basic unit– master-slave flip-flop– twice as much logic– output
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