University of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Sciences Lab 2 FPGA CAD Tool Flow 1. Motivation In this lab you will take a simple design through the FPGA Computer Aided Design (CAD) tool-flow, starting from design entry all the way to programming the hardware. This lab will give you experience with the software that you’ll be using for the rest of the semester. 2. Introduction to the Design Tool Flow Refer to the below illustration for the steps involved in the CAD tool flow we will use. 2.1 Design Entry The first step in logic design is to conceptualize your design. Once you have a good idea about the function and structure of your circuit and maybe drawn a block diagram or two, you can start the implementation process by specifying your circuit. In this class we will use a Hardware Description Language (HDL) called Verilog. HDLs have several advantages over other methods of circuit specification: ease of editing (files can be written using any text editor), ease of management when dealing with large designs, and the ability to use a high-level behavioral description of a circuit. If you are familiar with emacs, you may find it convenient for writing and editing Verilog code. In Lab 3 you will write Verilog; for lab 2 this week, we will provide you the appropriate Verilog descriptions. 2.2 Synthesis Once your design is entered, the next step in the implementation path is synthesis. In our case, the function of the synthesis program is to translate the Verilog description of the circuit into an equivalent circuit comprising a set of primitive circuit components that can be directly implemented on an FPGA. In a way, the synthesis tool is almost like a compiler. Where a compiler translates to a sequence of primitive commands that can bedirectly executed on a processor, synthesis translates to primitive circuit components that can be directly implemented in FPGA. The final product of a synthesis tool is a netlist file, a text file that contains a list of all the instances of primitive components in the translated circuit and a description of how they are interconnected. 2.3 Placement, Routing The next step in the implementation flow is to take the netlist of components generatedby the synthesis tool and turn it into bits that are need to configure the LUTs, Switchboxes, Flip-flops, and other configurable resources in the FPGA. To do that, first the primitive circuit components in the netlist need to be assigned to a specific place on the FPGA. For example, a 4LUT implementing the function of a 4 input NAND gate in a netlist could be implemented with any of the about 40,000 4LUTs in a Xilinx Virtex 2000E FPGA chip. Clever choice of placement will make the subsequent routing easier and result in a faster overall circuit. Once the components are placed, the proper connections must be made according to the netlist description. That step is called routing. Unlike synthesis, which only requires a set of primitive components to translate to; placement and routing are dependent upon the specific size and structure of the target FPGA chip. Due to this reliance, the FPGA vendor usually provides the placement and routing programs. The end product after placement and routing is a bit file containing the stream of bits used to configure the FPGA. Note: placement and routing are NP hard optimization problems and the provided software uses heuristics to solve them. There are cases where humans can do a better job by hand. 2.4 Program Hardware The last step in the implementation flow is the simple act of transporting the configuration bits to the FPGA. There are also many ways of doing this. For this class we will be mostly using the Parallel Cable IV along with the iMPACT software to program the board. In a finalized working product, the program will be loaded onto the FPGA probably at boot time from an onboard prom. 2.5 Verification As you should have learned from experience, a significant part of the time and effort used on any sizable project will be spent on debugging, and logic design is no exception. There are two ways to verify the correctness of a design: to program the FPGA with the design and check if the circuit is behaving correctly, or to run simulations of the design in software. To program the FPGA and physically check the functionality sounds simple and is in fact the final testing that a design must pass. However, the whole tool flow takes a while to run and repeatedly tweaking the input design to fix errors would require running the flow repeatedly. In addition it can be difficult to physically observe the causes for an error on a FPGA. For these reasons, software simulation is also needed in the verification process. There are many places along the tool flow where you can use simulation to verify the correctness of your design. For this class we will use an HDL simulator for all the different simulations. The first place to simulate your design is right after design entry. At this point you can only test functionality. Because there is no information available about the actual implementation on the FPGA, there is no way to accurately predict delay. As you progress down the tool flow and more information about the physical implementation on the FPGA becomes available, more accurate timingsimulations can be performed. The CAD tool at each step along the implementation flow is capable of producing Verilog files annotated with timing values that can be used in simulation. 3. Prelab 1. Read and understand the introduction to Design Tool Flow (above). 2. Take a look at the provided Verilog files to see if you can decipher them. (If you have not had experience with Verilog in the past, you will probably not understand everything in this files, but should be able to understand the basic function of the specified circuit and the operation of the tester.) http://inst.eecs.berkeley.edu/~cs150/handouts/3/Lab/lab2_cir.v http://inst.eecs.berkeley.edu/~cs150/handouts/3/Lab/lab2_cir_testbench.v 3. Read section 1,3,7,11 of the Modelsim tutorial. http://inst.eecs.berkeley.edu/~cs150/handouts/3/Lab/qk_guide.pdf 4 Procedure 4.2 Functional simulation 1. Download lab2_cir.v and lab2_cir_testbench.v from the course website. 2. Start the Modelsim simulator. 3. Create a new project and add the two provided files as existing files. 4. Compile both files. 5. Start a simulation of the lab2_cir_testbench module. 6.
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