Time TableMotivationSimulation in the CAD FlowPreLabLab ProcedureBasic Testbenches and ModelSim TutorialModelSim TutorialBasic Testbench EditingBroken Adder Exhaustive TestingBroken Adder Randomized TestingFSM MappingLab 4 CheckoffEECS150: Lab 4, Circuit Simulation and TestingUC Berkeley College of EngineeringDepartment of Electrical Engineering and Computer Science1 Time TableASSIGNED Friday, February 12ndDUE Week 6: February 23rd− 25th, during your assigned lab section2 Motivatio nThis lab will introduce the basics of simulation, an essential tool for debugging and verification. Sofar, we have lacked the ability to properly test our synthesized circuits before putting our designs ontothe FPGA. Although the circuits we have designed up to this point in class are relatively simple, youwill eventually be working with larger and larger designs. These may take up to half an hour to justsynthesize, place/route, and program onto an FPGA, making the current trial and error testing strategyquite impractical. In this lab, you will learn how to simulate a hardware design and write testbenches,both of which are essential in the verification process of large and com plex systems.3 Simulation i n the CAD FlowIn Labs 1 through 3, you have learned how to describe your design in high-level behavioral Verilog andobserved its functionality in hardware. Furthermore, you have gained insight into the roles of each toolin the CAD tool flow and better understoo d the underlying architecture of an FPGA. However, you havealso struggled with debugging and tes ting, due to a lack of visibility of the intermediate signals in yourdesign.This lab will introduce software simulation as a testing and debugging tool. Rather than writingsynthesizable Ve rilog like in Labs 2 and 3, you will instead be writing testbench oriented Verilog which,in general, cannot be mapp ed into actual hardware. By sacrificing the ability to synthesize the code,however, you gain the ability to use high-level Verilog constructs, such as for loops, while loops, andeven function calls, all to help simplify the simulation and verification process.4 PreLabPlease make sure to complete the prelab before you attend your lab section. This week’s lab will be verylong and frustrating if you do not do the prelab ahead of time.1. Read this entire handout thoroughly.• Pay particular attention to Section 5 as it describes in detail the circuits and testbenches thatyou will write and analyze2. Examine the Verilog provided for this weeks lab and answer the prelab questions.3. Write your Verilog ahead of time.1Figure 1 The CAD tool flow010110001001001101000101010100100101Translate/Map/PARFPGA EditorBitGen iMPACT.ncd.ncd.ncd (optionally modified).bitLogic SynthesisDesign EntryVerilog HDL Synplify ProOptional stepSimulationModelSim(a) Lab4BasicTestbench.v• Modify the testbench to provide the correct sequence of inputs to make the output of theDUT periodic over 3 cycles.• See Section 5.1 for details.(b) Lab4AdderTestbench.v• Write a testbench that exhaustively tests every possible input combination to the brokenadder and checks the output against a behavioral model• See Section 5.2 for details.• Write a version of this testbench to instead supply a stream of random inputs• See Section 5.3 for details(c) Lab4FSMTestbench.v• Write a testbench that will read input sequences from a file and apply inputs automaticallyto the state machine• See Section 5.4 for details.5 Lab Procedure5.1 Basic Testbenches and ModelSim TutorialLab4Basic.v implements the circuit shown in Figure 2, with a port specification defined in Table 1.Lab4BasicTestbench.v is a testbench verilog module. It is resp onsible for instantiating the DesignUnder Test (DUT, for short), Lab4Basic in this case, as well as controlling the values of the inputs tothe DUT. Please examine the code and complete the prelab section.5.1.1 ModelSim TutorialThis part of the lab is designed to acquaint you with ModelSim by simulating Lab4Basic throughrunning Lab4BasicTestbench.1. Launch Xili nx ISE and add all the relevant Ve rilog files.2. From within Xilinx ISE, select Behavioral Simulation from the Sources for: pull-down (seeFigure 3).2Figure 2 Lab4Basic Schematic diagramClockBCADQDQR1 R2OutInTable 1 Port Specification for Lab4Bas icSignal Width Dir DescriptionClock 1 I The Clock signalReset 1 I The system Reset signalIn 1 I The input signal to Lab4BasicOut 1 O Output signal from Lab4BasicFigure 3 Change the Sources to Behavioral Simulation33. Select Lab4BasicTestbench in the Sources box.4. This will change the Processes For Source box to show a number of steps involving ModelSim.Click on the + next to ModelSim Simulator and Double-click on the Simulate BehavioralModel process.(a) It may take ModelSim a few seconds to start up. When it does, you should see somethingresembling Figure 4.(b) ModelSim is composed of multiple windows: the Transcript Window showing text messagesboth from the ModelSim tools and anything printed by the circuit you are simulating, WaveWindow showing the waveforms from your testbench and any other signals you choose,Objects Window which lists the signals in the currently selected module allowing you todrag them to the Wave Wi ndow, and Workspace Window which will let you navigatethe tree of modules in your project to change the contents of the Objects Window.Figure 4 The ModelSim simulator. The Transcript Window is outlined in blue, the Wave Windowis in gold. The Objects Window is in green, and the Workspace Window is in Red5. Like Synplify Pro, ModelSim will syntax check your code and any errors or warnings will showup in the Transcript Window.6. The Wave Window is where you will be spending a good majority of your time in, so let us takea moment and familiarize yourself with it.(a) You can click the magnifying glass buttons to zoom in or out.(b) The signal values listed in the second column are those at the vertical yellow cursor.i. Move the cursor by simply clicking in the wave window.ii. To see the s ignal values in hexadecimal select one or more signals, right-click and s elec tRadix → Hexadecimal.(c) You will probably want to undock and maximize the Wave Window.47. By default, ModelSim adds only the signals from the testbench to the Wave Window. Thus, wewill need to add the signals A, B, C from Lab4Basic ourselves.(a) Go to the ModelSim Workspace Window.(b) Navigate the module tree to the DUT instance.(c) Right-Click on that module and select Add → To
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