EECS 150 - Components and Design Techniques for Digital SystemsLec 8 – Timing Intro, KMAP, SynthesisDavid CullerElectrical Engineering and Computer SciencesUniversity of California, Berkeleyhttp://www.eecs.berkeley.edu/~cullerhttp://inst.eecs.berkeley.edu/~cs1509/20/07 EECS 150, Fa07, Lec 08-timing-synth2Outline• Timing Methodology for Synchronous Circuits• Boolean Logic minimization (Kmaps)• Synthesis – what else the tools do [to the extent time permits]9/20/07 EECS 150, Fa07, Lec 08-timing-synth3Review: Fundamental Design Principle• Divide circuit into combinational logic and state• Localize feedback loops and make it easy to break cycles• Implementation of storage elements leads to various forms of sequential logicCombinationalLogicStorage ElementsOutputsState OutputsState InputsInputs9/20/07 EECS 150, Fa07, Lec 08-timing-synth4Recall: What makes Digital Systems tick?CombinationalLogictimeclk9/20/07 EECS 150, Fa07, Lec 08-timing-synth5Timing Methodology• Rules for interconnecting components and clocks– Guarantee proper operation of system when strictly followed• Approach depends on building blocks used for storage elements– Focus on systems with edge-triggered flip-flops» Found in programmable logic devices– Many custom integrated circuits focus on level-sensitive latches• Basic rules for correct timing:– (1) Correct inputs, with respect to time, are provided to the flip-flops» Everything is stable when the clock ticks– (2) No flip-flop changes state more than once per clocking event9/20/07 EECS 150, Fa07, Lec 08-timing-synth6there is a timing "window" around the clocking event during which the input must remain stable and unchanged in order to be recognizedclockdatachangingstableinputclockTsuThclockdataDQ DQTiming Methodologies (cont’d)• Definition of terms– clock: periodic event, causes state of storage element to change; can be rising or falling edge, or high or low level– setup time: minimum time before the clocking event by which the input must be stable (Tsu)– hold time: minimum time after the clocking event until which the input must remain stable (Th)9/20/07 EECS 150, Fa07, Lec 08-timing-synth7behavior is the same unless input changeswhile the clock is highDQCLKpositiveedge-triggeredflip-flopDQGCLKtransparent(level-sensitive)latchDCLKQedgeQlatchComparison of Latches and Flip-Flops9/20/07 EECS 150, Fa07, Lec 08-timing-synth8all measurements are made from the clocking event, i.e.the rising edge of the clockTypical Timing Specifications• Positive edge-triggered D flip-flop– Setup and hold times– Minimum clock width– Propagation delays (low to high, high to low, max and typical)Th5nsTw 25nsTplh25ns13nsTphl40ns25nsTsu20nsDCLKQTsu20nsTh5ns9/20/07 EECS 150, Fa07, Lec 08-timing-synth9INQ0Q1CLK100Cascading Edge-triggered Flip-Flops• Shift register– New value goes into first stage– While previous value of first stage goes into second stage– Consider setup/hold/propagation delays (prop must be > hold)CLKINQ0 Q1DQ DQ OUT9/20/07 EECS 150, Fa07, Lec 08-timing-synth10timing constraintsguarantee properoperation ofcascaded componentsassumes uniform distribution of the clockCascading Edge-triggered Flip-Flops • Why this works– Propagation delays exceed hold times– Clock width constraint exceeds setup time– This guarantees following stage will latch current value before it changes to new valueTsu4nsTp3nsTh2nsInQ0Q1CLKTsu4nsTp3nsTh2nsTp+ Tsu< TclkTp> Th9/20/07 EECS 150, Fa07, Lec 08-timing-synth11INQ0Q1CLK100Cascading Edge-triggered Flip-Flops• Shift register– New value goes into first stage– While previous value of first stage goes into second stage– Consider setup/hold/propagation delays (prop must be > hold)CLKINQ0 Q1DQ DQ OUTDelayClk1Clk19/20/07 EECS 150, Fa07, Lec 08-timing-synth12original state: IN = 0, Q0 = 1, Q1 = 1due to skew, next state becomes: Q0 = 0, Q1 = 0, and not Q0 = 0, Q1 = 1CLK1 is a delayedversion of CLK0InQ0Q1CLK0CLK1100Clock Skew• The problem– Correct behavior assumes next state of all storage elementsdetermined by all storage elements at the same time– Difficult in high-performance systems because time for clock to arrive at flip-flop is comparable to delays through logic (and will soon become greater than logic delay)– Effect of skew on cascaded flip-flops:9/20/07 EECS 150, Fa07, Lec 08-timing-synth13timing constraintsguarantee properoperation ofcascaded componentsassumes uniform distribution of the clockCascading Edge-triggered Flip-Flops • Why this works (redux)– Propagation delays exceed hold times– Clock width constraint exceeds setup time– This guarantees following stage will latch current value before it changes to new valueTsu4nsTp3nsTh2nsInQ0Q1CLKTsu4nsTp3nsTh2nsTp+ Tsu+ Tskew< TclkTp-Tskew> Th9/20/07 EECS 150, Fa07, Lec 08-timing-synth14Type When inputs are sampled When output is validunclocked always propagation delay from input changelatchlevel-sensitive clock high propagation delay from input changelatch (Tsu/Th around falling or clock edge (whichever is later)edge of clock)master-slave clock high propagation delay from falling edgeflip-flop (Tsu/Th around falling of clockedge of clock)negative clock hi-to-lo transition propagation delay from falling edgeedge-triggered (Tsu/Th around falling of clockflip-flop edge of clock)Comparison of Latches and Flip-Flops9/20/07 EECS 150, Fa07, Lec 08-timing-synth15Summary of Latches and Flip-Flops• Development of D-FF– Level-sensitive used in custom integrated circuits» can be made with 4 switches– Edge-triggered used in programmable logic devices– Good choice for data storage register• Historically J-K FF was popular but now never used– Similar to R-S but with 1-1 being used to toggle output (complement state)– Good in days of TTL/SSI (more complex input function: D = JQ' + K'Q– Not a good choice for PLAs as it requires two inputs– Can always be implemented using D-FF• Preset and clear inputs are highly desirable on flip-flops– Used at start-up or to reset system to a known state9/20/07 EECS 150, Fa07, Lec 08-timing-synth16Logic Minimization• One piece of synthesis9/20/07 EECS 150, Fa07, Lec 08-timing-synth17Quick Review: Canonical Forms• Standard form for a Boolean expression - unique algebraic expression directly from a true table (TT) description.• Two Types:* Sum of Products (SOP)* Product of Sums (POS)• Sum of Products (disjunctive normal form, minterm expansion). Example:minterms a b
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