ObjectivesPrelabHigh-level SpecificationLow-level specificationBusesForcing Internal SignalsClocksCommand and Log FilesNamingCheckoffs: Lab 2University of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Science EECS 150 Original Lab By: J.Wawrzynek and N. Weaver Spring 2001 Later revisions by R. Fearing, and J. Shih Xilinx Foundation 3.0 version: Laura Todd Lab 2 Finite State Machine 1 Objectives You will enter and debug a Finite State Machine (FSM). Using our definition of the problem and logic equations specifying the FSM’s operation, you will enter your design in the schematic editor and simulate it with the logic simulator. 2 Prelab • Get a partner from your lab section! • Complete your IN1 (INput 1) and IN2 (INput 2) blocks • Write a .cmd (command) file to test your CLB (Combinational Logic Block). • Write one single .cmd file with all the FSM test scenarios specified in the check-off sheet. • Do as much as possible before your scheduled lab time. There is much to do in this lab. Some can be done on paper; the remainder can be done on the computers outside of lab time. 3 High-level Specification You are building the controller for a 2-bit serial lock used to control entry to a locked room. The lock has a RESET button, an ENTER button, and two two-position switches, CODE1 and CODE0, for entering the combination. For example, if the combination is 01-11, someone opening the lock would first set the two switches to 01 (CODE1 = low, CODE0 = high) and press ENTER. Then s/he would set the two switches to 11 (CODE1 = high, CODE0 = high) and press ENTER. This would cause the circuit to assert the OPEN signal, causing an electromechanical relay to be released and allowing the door to open. Our lock is insecure with only sixteen different combinations; think about how it might be extended. If the person trying to open the lock makes a mistake entering the switch combination, s/he can restart the process by pressing RESET. If s/he enters a wrong sequence, the circuitry would assert the ERROR signal, illuminating an error light. S/he must press RESET to start the process over. In this lab, you will enter a design for the lock’s controller in a new Xilinx project. Name this lab “lab2”. Make RESET and ENTER inputs. Simulate by pressing the ENTER button by forcing it high for a clock cycle. Use a two-bit wide input bus called CODE[1:0] for the two switches. (Information on how to use buses will be given later in this handout). The outputs are an OPEN signal and an ERROR signal. Figure 1 shows a decomposition of the combination lock controller, whose inputs and outputs are: Input Signal Description RESET Clear any entered numbers ENTER Read the switches (enter a number in the combination) CODE[1:0] Two binary switches Output signal Description OPEN Lock opens ERROR Incorrect combinationFigure 1: Controller for the combination lock Figure 2: State Transition Diagram 4 Low-level specification 4.1 IN1 (INput 1) and IN2 (INput 2) Blocks IN1 and IN2 process the input signals COM1 (COMpare 1) and COM2 (COMpare 2) into a simpler form for the FSM. Specifically, COM1 is asserted when CODE[1:0] is the combination’s first number. Similarly, COM2 is asserted for the second number. Partitioning the circuit in this way makes the combination easy to change. Choose your own combination; the two numbers must be different. This should be a simple block. Use a few AND gates and inverters.4.2 MYCLB The MYCLB (MY Combinational Logic Block) block takes RESET, ENTER, COM1, COM2, and present state and generates OPENLOCK and ERROR, as well as the next state. Figure 2 shows the state transition diagram, a Mealy machine since the transitions are labeled with both inputs and outputs. The white circle denotes the rest state (i.e., the state the machine starts in). RESET ENTER COM1 COM2 S[2:0] NS[2:0] ERROR OPEN 1 X X X XXX 000 0 0 0 0 X X 000 000 0 0 0 1 0 X 000 101 0 0 0 1 1 X 000 001 0 0 0 0 X X 001 001 0 0 0 1 X 0 001 110 0 0 0 1 X 1 001 010 0 0 0 X X X 010 010 0 1 0 0 X X 101 101 0 0 0 1 X X 101 110 0 0 0 X X X 110 110 1 0 Figure 3: Truth Table for the FSM = TEMP0 = RESET’ S1 S0’TEMP1 = RESET’ S1’TEMP2 = ENTER S2’ S0’TEMP3 = ENTER’ S0 + TEMP2TEMP4 = COM2’ ENTER + S2TEMP5 = ENTER S0’TEMP6 = COM1’ TEMP5 + TEMP4 S0ERROR = S2 TEMP0OPEN = S2’ TEMP0NS0 = TEMP1 TEMP3NS1 = TEMP0 + ENTER TEMP1 S0NS2 = ERROR + TEMP1 TEMP6ERROR = RESET’ S2 S1 S0’OPEN = RESET’ S2’ S1 S0’NS0 = RESET’ ENTER COM1’ S2’ S1’ S0’ +RESET’ ENTER COM1 S2’ S1’ S0’ +RESET’ ENTER’ S2’ S1’ S0 +RESET’ ENTER’ S2 S1’ S0NS1 = RESET’ ENTER COM2’ S2’ S1’ S0 +RESET’ ENTER COM2 S2’ S1’ S0 +RESET’ S2’ S1 S0’ +RESET’ ENTER S2 S1’ S0 +RESET’ S2 S1 S0’NS2 = RESET’ ENTER’ COM1’ S2’ S1’ S0’ +RESET’ ENTER COM2’ S2’ S1’ S0 +RESET’ ENTER’ S2 S1’ S0 +RESET’ ENTER S2 S1’ S0 +RESET’ S2 S1 S0’ (a) (b) Figure 4: Logic Equations for the FSM (Unoptimized): (a) two-level (b) multi-level By writing an “AND” term describing each row where an output is 1 and ORing these together, it’s easy to obtain a set of equations implementing the table shown in Figure 3. Translating a state transition diagram to a truth table is mechanical: Write a row for each transition. In Figure 4a, I’ve collapsed a few rows together by noting that when RESET is 1, the outputs and next state are the same for all states. Note RESET’ means NOT RESET. Implementing the equations of Figure 4a as written would be inefficient, so we introduce intermediate variables TEMP0, ..., TEMP6 as shown in Figure 4b. Make symbol and schematic for MYCLB using the equations in Figure 4b. 4.3 MYDFF (MY D Flip-Flops) Create a block called MYDFF that contains three D flip-flops (one for each state bit) with an asynchronous clear hooked to a pin called FFRESET (Flip-Flop RESET). The flip-flops you should use are the FDR (D Flip-flop with synchronous Reset) flip-flops. Externally, connect FFRESET to 0 (i.e., not resetting), but during simulation you can force this to 1 to reset every flip-flop.5 Buses 5.1 Definition and Usefulness Buses are collections of ordered wires that (for one reason or another) were collected in a group for easy reference. Examples of busses include the two input bits of our combination lock
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