Spring 2009EECS150 - Lec24-blocksPage EECS150 - Digital DesignLecture 23 - FFs revisited, FIFOs, ECCs, LSFRsApril 16, 2009John Wawrzynek1Spring 2009EECS150 - Lec24-blocksPage Cross-coupled NOR gates• If both R=0 & S=0, then cross-couped NORs equivalent to a stable latch:• If either R or S becomes =1 then state may change:• What happens if R or S or both become = 1?remember,2Spring 2009EECS150 - Lec24-blocksPage Asynchronous State Transition DiagramSR Latch:• S is “set” input• R is “reset” inputQQ’=00 is often called a “forbidden state”Transitions triggered by input changes.3Spring 2009EECS150 - Lec24-blocksPage Nand-gate based SR latch• Same behavior as cross-coupled NORs with inverted inputs.4Spring 2009EECS150 - Lec24-blocksPage Level-sensitive SR Latch• The input “C” works as an “enable” signal, latch only changes output when C is high.• usually connected to clock.• Generally, it is not a good idea to use a clock as a logic signal (into gates etc.). This is a special case.5Spring 2009EECS150 - Lec24-blocksPage D-latchCompare to transistor version:6All state elements could be built using logic gates.Spring 2009EECS150 - Lec24-blocksPage Flip-flops7Spring 2009EECS150 - Lec24-blocksPage J-K FF• Add logic to eliminate “indeterminate” action of RS FF.• New action is “toggle”• J = “jam”• K = “kill”JKQclk8Spring 2009EECS150 - Lec24-blocksPage Storage Element Taxonomy synchronous asynchronous level-sensitive edge-triggeredD-type n.a.JK-type n.a.RS-type “latch” “flip-flop” “latch”“natural” form “possible” form9Spring 2009EECS150 - Lec24-blocksPage Design Example with RS FF• With D-type FF state elements, new state is computed based on inputs & present state bits - reloaded each cycle.• With RS (or JK) FF state elements, inputs are used to determine conditions under which to set or reset state bits.• Example: bit-serial adder (LSB first)With D-FF for carry10Spring 2009EECS150 - Lec24-blocksPage Bit-serial adder with RS FF• RS FF stores the carry:a b ci ci+1 sCarry kill a’b’Carry generateab11Spring 2009EECS150 - Lec24-blocksPage FIFOs12Spring 2009 EECS150 – Lec24-blocksPage First-in-first-out (FIFO) Memory• Used to implement queues. • These find common use in computers and communication circuits.• Generally, used for rate matching data producer and consumer:• Producer can perform many writes without consumer performing any reads (or vis versa). However, because of finite buffer size, on average, need equal number of reads and writes.• Typical uses: – interfacing I/O devices. Example network interface. Data bursts from network, then processor bursts to memory buffer (or reads one word at a time from interface). Operations not synchronized.– Example: Audio output. Processor produces output samples in bursts (during process swap-in time). Audio DAC clocks it out at constant sample rate.stating stateafter writeafter readSpring 2009 EECS150 – Lec24-blocksPage FIFO Interfaces• After write or read operation, FULL and EMPTY indicate status of buffer.• Used by external logic to control own reading from or writing to the buffer.• FIFO resets to EMPTY state.• HALF FULL (or other indicator of partial fullness) is optional.• Address pointers are used internally to keep next write position and next read position into a dual-port memory.•If pointers equal after write ⇒ FULL:•If pointers equal after read ⇒ EMPTY:DINDOUTWEREEMPTYFULLHALF FULLRST CLKFIFOwrite ptrread ptrwrite ptr read ptrwrite ptr read ptrSpring 2009 EECS150 – Lec24-blocksPage FIFO Implementation Details WE RE equal EMPTYi FULLi 0 0 0 0 0 0 0 1 EMPTYi-1 FULLi-1 0 1 0 0 0 0 1 1 1 0 1 0 0 0 0 1 0 1 0 1 1 1 0 0 0 1 1 1 EMPTYi-1 FULLi-1 • Assume, dual-port memory with asynchronous read, synchronous write.• Binary counter for each of read and write address. CEs controlled by WE and RE.• Equal comparator to see when pointers match.• Flip-flop each for FULL and EMPTY flags: • Control logic with truth-table shown to left.Spring 2009 EECS150 – Lec24-blocksPage Xilinx Virtex5 FIFOs• Virtex5 BlockRAMS include special logic for FIFOs.• Details in User Guide (ug190).• Take advantage of separate dual ports and independent ports clocks.Spring 2009 EECS150 – Lec24-blocksPage ECCsSpring 2009 EECS150 – Lec24-blocksPage Error Correction Codes (ECC)• Memory systems generate errors (accidentally flipped-bits)– DRAMs store very little charge per bit– “Soft” errors occur occasionally when cells are struck by alpha particles or other environmental upsets.– Less frequently, “hard” errors can occur when chips permanently fail.• Where “perfect” memory is required– servers, spacecraft/military computers, …• Memories are protected against failures with ECCs• Extra bits are added to each data-word– extra bits are used to detect and/or correct faults in the memory system– in general, each possible data word value is mapped to a unique “code word”. A fault changes a valid code word to an invalid one - which can be detected.Spring 2009 EECS150 – Lec24-blocksPage Simple Error Detection Coding• Each data value, before it is written to memory is “tagged” with an extra bit to force the stored word to have even parity:• Each word, as it is read from memory is “checked” by finding its parity (including the parity bit). Parity Bitb7b6b5b4b3b2b1b0p+b7b6b5b4b3b2b1b0p+c• A non-zero parity indicates an error occurred:– two errors (on different bits) is not detected (nor any even number of errors)– odd numbers of errors are detected.Spring 2009 EECS150 – Lec24-blocksPage Hamming Error Correcting Code• Use more parity bits to pinpoint bit(s) in error, so they can be corrected.• Example: Single error correction (SEC) on 4-bit data – use 3 parity bits, with 4-data bits results in 7-bit code word– 3 parity bits sufficient to identify any one of 7 code word bits– overlap the assignment of parity bits so that a single error in the 7-bit word
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