Spring 2009EECS150 - Lec03-FPGAPage EECS150 - Digital DesignLecture 3 - Field Programmable Gate Arrays (FPGAs)January 27, 2009John Wawrzynek1Spring 2009EECS150 - Lec03-FPGAPage FPGA Overview• Basic idea: two-dimensional array of logic blocks and flip-flops with a means for the user to configure (program): 1. the interconnection between the logic blocks, 2. the function of each block.Simplified version of FPGA internal architecture:2Spring 2009EECS150 - Lec03-FPGAPage Die Photos: Virtex FPGA vs. Pentium IV• FGPA Vertex chip looks remarkably structured– Very dense, very regular structure• “Full-Custom” Pentium chip somewhat more random in structure– Large on-chip memories (caches) are visible3Spring 2009EECS150 - Lec03-FPGAPage Xilinx Technology Drives Performance in BMW Williams Formula One Race Car at 2003 Grand PrixSep 26, 2003 18:08 ET Xilinx-Enabled WilliamsF1 BMW FW25 Challenges Ferrari for the Win Xilinx-Enabled WilliamsF1 (PRNewsFoto)SAN JOSE, Calif., Sept. 26 /PRNewswire/ -- At the Indianapolis 2003 Grand Prix today, Xilinx, Inc. (NASDAQ:XLNX) programmable chips will play a mission-critical role in the performance of the BMW WilliamsF1 Team. The BMW WilliamsF1 Team is the leading contender in the 2003 Formula One Series, currently heading the FIA Formula One Constructors' Championship. After a closely fought race in Monza, Italy, between Ferrari, BMW Williams and McLaren, the outcome of today's U.S. Grand Prix race could hold the key to the entire 2003 FIA Formula One Championship. The season concludes with a final race in Suzuka, Japan on October 12. The teams and drivers who remain in contention are acutely conscious that wins and losses will come at the margins of performance, and no one can afford anything less than a faultless race. The BMW WilliamsF1 Team selected high performance programmable chips from Xilinx as the leading technology in the Vehicle Control Module (VCM) of the team's 2003 Challenger -- the WilliamsF1 BMW FW25. The Xilinx-enabled VCM is used to control essential vehicle components such as the gearbox, differential, traction control, launch control and telemetry. With leading edge technology -- greater on-chip functionality and lower power consumption, Xilinx FPGAs have ensured that the VCM unit is reduced in size and weight, ultimately enhancing the performance of the car.FPGA also get used in many (not as interesting) products: network routers, set-top boxes, printers, etc.Far more designs are implemented in FPGA than in custom chips.4Spring 2009EECS150 - Lec03-FPGAPage FPGA Variations• Families of FPGA’s differ in:– physical means of implementing user programmability,– arrangement of interconnection wires, and– the basic functionality of the logic blocks.• Most significant difference is in the method for providing flexible blocks and connections: • Anti-fuse based (ex: Actel)+ Non-volatile, relatively small– fixed (non-reprogrammable)5Spring 2009EECS150 - Lec03-FPGAPage User Programmability• Latches are used to:1. make or break cross-point connections in the interconnect2. define the function of the logic blocks3. set user options:• within the logic blocks• in the input/output blocks• global reset/clock• “Configuration bit stream” can be loaded under user control• Latch-based (Xilinx, Altera, …)+ reconfigurable– volatile– relatively large.6Spring 2009EECS150 - Lec03-FPGAPage Idealized FPGA Logic Block• 4-input look up table (LUT)– implements combinational logic functions• Register– optionally stores output of LUT7Spring 2009EECS150 - Lec03-FPGAPage Background for Next Slide• A MUX or multiplexor is a combinational logic circuit that chooses between 2N inputs under the control of N control signals.• A latch is a 1-bit memory (similar to a flip-flop).8Spring 2009EECS150 - Lec03-FPGAPage 4-LUT Implementation• n-bit LUT is implemented as a 2n x 1 memory:– inputs choose one of 2n memory locations.– memory locations (latches) are normally loaded with values from user’s configuration bit stream.– Inputs to mux control are the CLB inputs.• Result is a general purpose “logic gate”. – n-LUT can implement any function of n inputs!9Spring 2009EECS150 - Lec03-FPGAPage LUT as general logic gate• An n-lut as a direct implementation of a function truth-table.• Each latch location holds the value of the function corresponding to one input combination.Example: 4-lutExample: 2-lutImplements any function of 2 inputs. How many of these are there?How many functions of n inputs?10Spring 2009EECS150 - Lec03-FPGAPage FPGA Generic Design Flow• Design Entry:– Create your design files using:• schematic editor or • HDL (hardware description languages: Verilog, VHDL)• Design Implementation:– Logic synthesis, in case of using HDL entry followed by,–Partition, place, and route to create configuration bit-stream file• Design verification:– Optionally use simulator to check function,– Load design onto FPGA device (cable connects PC to development board)11Spring 2009EECS150 - Lec03-FPGAPage Example Partition, Placement, and Route• Example Circuit:– collection of gates and flip-flops• Idealized FPGA structure:Circuit combinational logic must be “covered” by 4-input 1-output LUTs.Flip-flops from circuit must map to FPGA flip-flops. (Best to preserve “closeness” to CL to minimize wiring.)Best placement in general attempts to minimize wiring.12Vdd, GND, clock, and global resets are all “prewired”.Spring 2009EECS150 - Lec03-FPGAPage Example Partition, Placement, and Route• Example Circuit:– collection of gates and flip-flops13Two partitions. Each has single output, no more than 4 inputs, and no more than 1 flip-flop. In this case, inverter goes in both partitions. Note: the partition can be arbitrarily large as long as it has not more than 4 inputs and 1 output, and no more than 1 flip-flop.AABBINOUTSpring 2009EECS150 - Lec03-FPGAPage Xilinx FPGAs (interconnect detail)14Spring 2009EECS150 - Lec03-FPGAPage Project platform: Xilinx ML505-11015Spring 2009EECS150 - Lec03-FPGAPage FPGA: Xilinx Virtex-5 XC5VLX110TVirtex-5 “die photo” A die is an unpackaged part !"#$%&'()*$$+,,-$$$).'/0$1!"#$%&'&()*+#',$ #-$ ./0123.445+6)*+#'7/4&6+-+6$0#895)($12#6: .(6;+*&6*9(&<!"#$%&'()*!"#$%&'(!"#$%&')16Spring 2009EECS150 - Lec03-FPGAPage From die to PC board ...!"#$%&'()*$$+,,-$$$).'/0$1!"#$%&'&()*+#',$#-$./0123.445+6)*+#'7/4&6+-+6$0#895)($12#6:
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