1Fall 2011 EECS150 Lecture 5Page 1EECS150 - Digital DesignLecture 5 – Verilog & SynthesisSeptember 8, 2011Elad AlonElectrical Engineering and Computer SciencesUniversity of California, Berkeleyhttp://www-inst.eecs.berkeley.edu/~cs150Fall 2011 EECS150 Lecture 5Page 2Announcements• Homework #1 due today– Drop box in 240 Cory• Homework #2 out tonight– Due next Thurs.2Fall 2011 EECS150 Lecture 5Page 3Example: Variable Counter Fall 2011 EECS150 Lecture 5Page 4Parameterized Version3Fall 2011 EECS150 Lecture 5Page 5Generate LoopPermits variable declarations, modules, user defined primitives,gate primitives, continuous assignments, initial blocks and always blocks to be instantiated multiple times using a for-loop.// Gray-code to binary-code convertermodule gray2bin1 (bin, gray); parameter SIZE = 8; output [SIZE-1:0] bin; input [SIZE-1:0] gray; genvar i; generate for (i=0; i<SIZE; i=i+1) begin:bitassign bin[i] = ^gray[SIZE-1:i]; end endgenerateendmoduleLoop must have constant boundsgenerate if-else-if based on an expression that is deterministic at the time the design is synthesized.generate case : selecting case expression must be deterministic at the time the design is synthesized. genvar exists only in the specification - not in the final circuit.Keywords that denote synthesis-time operationFor-loop creates instances of assignmentsFall 2011 EECS150 Lecture 5Page 6Logic SynthesisHDLSpecificationHierarchically define structure and/or behavior of circuit.SimulationFunctional verification.SynthesisMaps specification to resources of implementation platform (FPGA for us).4Fall 2011 EECS150 Lecture 5Page 7Logic Synthesis • Verilog and VHDL started out as simulation languages, but quickly people wrote programs to automatically convert Verilog code into low-level circuit descriptions (netlists).• Synthesis converts Verilog (or other HDL) descriptions to implementation technology specific primitives:– For FPGAs: LUTs, flip-flops, and RAM blocks– For ASICs: standard cell gate and flip-flop libraries, and memory blocks.Fall 2011 EECS150 Lecture 5Page 8Why Logic Synthesis?1. Automatically manages many details of the design process:Æ Fewer bugsÆ Improved productivity2. Abstracts the design data (HDL description) from any particular implementation technology.– Designs can be re-synthesized targeting different chip technologies. Ex: first implement in FPGA then later in ASIC.3. In some cases, leads to a more optimal design than could be achieved by manual means (ex: logic optimization)Why Not Logic Synthesis?1. May lead to non-optimal designs in some cases.5Fall 2011 EECS150 Lecture 5Page 9Main Logic Synthesis StepsParsing and Syntax CheckParsing and Syntax CheckDesign ElaborationDesign ElaborationInference and Library SubstitutionInference and Library SubstitutionLogic ExpansionLogic ExpansionLogic OptimizationLogic OptimizationPartition, Place & RoutePartition, Place & RouteLoad in HDL file, run macro preprocessor for `define, `include, etc..Compute parameter expressions, process generates, create instances, connect ports.Recognize and insert special blocks (memory, flip-flops, arithmetic structures, ...)Expand combinational logic to primitive Boolean representation.Apply Boolean algebra and heuristics to simplify and optimize under constraints.CL to LUTs, map memory and state elements to chip, assign physical locations, route connections.foo.vfoo.ncdFall 2011 EECS150 Lecture 5Page 10Operators and Synthesis• Logical operators map into primitive logic gates• Arithmetic operators map into adders, subtractors, …– Unsigned 2s complement– Model carry: target is one-bit wider that source– Watch out for *, %, and /• Relational operators generate comparators• Shifts by constant amount are just wire connections– No logic involved• Variable shift amounts a whole different story --- shifter• Conditional expression generates logic or MUXY = ~X << 2X[3]Y[0]Y[1]Y[2]X[0]X[1]X[2]Y[3]Y[4]Y[5]6Fall 2011 EECS150 Lecture 5Page 11Simple ExampleFall 2011 EECS150 Lecture 5Page 12Some More Interesting Examplesmodule mux4to1 (out, a, b, c, d, sel);output out;input a, b, c, d;input [1:0] sel;reg out;always @(sel or a or b or c or d)begincase (sel)2'd0: out = a;2'd1: out = b;2'd3: out = d;endcaseendendmodule7Fall 2011 EECS150 Lecture 5Page 13To avoid synthesizing a latch in this case, add the missing select line:2'd2: out = c;Or, in general, use the “default” case:default: out = foo;If you don’t care about the assignment in a case (for instance you know that it will never come up) then you can assign the value “x” to the variable. Example:default: out = 1‘bx;The x is treated as a “don’t care” for synthesis and will simplify the logic. Be careful when assigning x (don’t care). If this case were to come up, then the synthesized circuit and simulation may differ.Fix (Rule #1 for CL Always Blocks)Fall 2011 EECS150 Lecture 5Page 14module and_gate (out, in1, in2);input in1, in2;output out;reg out;always @(in1) beginout = in1 & in2;endendmoduleAnother Example8Fall 2011 EECS150 Lecture 5Page 15module and_gate (out, in1, in2);input in1, in2;output out;reg out;always @(in1) beginout = in1 & in2;endendmoduleIncomplete TriggersLeaving out an input trigger usually results in latch generation for the missing trigger.Easy way to avoid incomplete triggers for combinational logic is with:always @*Fall 2011 EECS150 Lecture 5Page 16Procedural Assignments• Blocking procedural assignment “=“– In simulation the RHS is executed and the assignment is completed before the next statement is executed. • Non-blocking procedural assignment “<=“– In simulation the RHS is executed and all assignment take place at the same time (end of the current time step - not clock cycle). Verilog has two types of assignments within always blocks:9Fall 2011 EECS150 Lecture 5Page 17Synthesized Procedural Assignmentsalways @ (posedge clk) begin always @ (posedge clk) begina = in; b = a; a <= in; b<= a; end endFall 2011 EECS150 Lecture 5Page 18Procedural AssignmentsThe sequential semantics of the blocking assignment allows variables to be multiply assigned within a single always block. Unexpected behavior can result from mixing these assignments in a single block. Standard rules:i. Use blocking assignments to model combinational logic within an always block ( “=”).ii. Use non-blocking assignments to implement
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