R. FearingCS150 Fall 1999 Lecture 7 Copyright © 1999 The Regents of the University of California0Admin1 Recap2 Loadable counter3 Design example: Walk light1 RECAP – Xilinx FPGADQ01DClockCEFDRECLBIoB(4 input) LutIN FF IBUFOUT FF OBUF01YABSYSASB+⋅=clockable FFMUX 2:1M2122 DFFR. FearingCS150 Fall 1999 Lecture 7 Copyright © 1999 The Regents of the University of California2 LOADABLE COUNTERFor (i = 0, i < N; i++)//DQNclock/OUT1N++01DQLoadclockINPUT/+1//R. FearingCS150 Fall 1999 Lecture 7 Copyright © 1999 The Regents of the University of California2 Loadable Counter (cont.)2.1 Xilinx library part ×74_163 (note: synchronous clear)Note: All CB4 parts are asynchronous!A QAB QBD QDC QCR RCOENP E NTcountclockLSBMSBripple carry outCLEAR.LLOAD.LLoad2.1.1 State diagram – very flexible – “branch counter”201. . .L(D=0)L(D=2)countcountR. FearingCS150 Fall 1999 Lecture 7 Copyright © 1999 The Regents of the University of California3 DESIGN EXAMPLE:Crosswalk ControlProblem:Design FSM controller so that traffic light turns yellow whenButton asserted. Yellow for 4 sec., Red for 2 sec., then REDand walk for 8 seconds. Given 1 Hz clock. Assume Buttonsynchronized. Use Moore machine.RYGwalkwalkButtonGivenR. FearingCS150 Fall 1999 Lecture 7 Copyright © 1999 The Regents of the University of California3 Design Example (cont.)Step 1. Block Diagram. Inputs?Button outputs: R, G, Y, walkFSMWALKYGRclockButtonStep 2. State diagram/Moore machineGY0Y3R9Y2Y1R3 R2R0R1R6R5 R4R8R7ButtonButtonR. FearingCS150 Fall 1999 Lecture 7 Copyright © 1999 The Regents of the University of California3 Design Example (cont.)Step 3. Block diagramButton Q3Q2Q1Q0ENP,T Reset.L Comment0 0 0 0 hold1X100 0001…1101 10X 111X 1 1 resetStep 4. State transition tableLogicCTRENP,T QResetclockButtonQ= 0?7Q14≤≤1Q4≤≤5Q14≤≤Moore MachineWYGR/CLB estimate - output decoders 2 CLB/input logic probably merged into CLBCTR ~ 4 CLB1230123QQQL.RESET , QQQQButtonENP ⋅⋅=++++=R. FearingCS150 Fall 1999 Lecture 7 Copyright © 1999 The Regents of the University of California3 Design Example (cont.)3.2 Alternate DesignIllustrates: Almost one hot encoding ⇒ glitch-free outputsEliminate output decoders – fewer CLBs for logiccombining FSMs ⇒ more CLBs for FFFS MWALKYGRclockButton/CTREN Q,Step 1. Block diagramR. FearingCS150 Fall 1999 Lecture 7 Copyright © 1999 The Regents of the University of California3 Design Example (cont.)Step 2. State diagramState assignment G Y R W01463211 10591413 1278ButtonButtonEQRESETEQEQCNTRR0GYButtonR1EQ140011001001001000EQ6EQ3FSMNo unique solution – always different tradeoffs, time, space, ...R. FearingCS150 Fall 1999 Lecture 7 Copyright © 1999 The Regents of the University of California3 Design Example (cont.)Step 3. Block diagramClockDQDQDQDQFSMDGDYDRDWQGQYQRQWNSD//ButtonQEQODQENsame as beforeQ2Q0Q1Q2Q3Q1RESET.LQ3CTRENPDRclockEQ14ENP Button Q3Q2Q1Q0++++=RESET.L Q3Q2Q1=R. FearingCS150 Fall 1999 Lecture 7 Copyright © 1999 The Regents of the University of California3 Design Example (cont.)Step 4. State transition tableINButton EQ QGPSQY QR QWNSQG OY QR QWComment0 X 11 X 1X 0 0X 1 0X 0 0X 1 0X 0 0X 1 00 0 00 0 01 0 01 0 00 1 00 1 00 1 10 1 11 0 0 00 1 0 00 1 0 00 0 1á 00 0 1á 00 0 1á 10 0 1á 11 0 0 0holdg Å yholdy Å rholdr Å wholdw Å gWatch out! 12 bogus states:fatal11111001LR. FearingCS150 Fall 1999 Lecture 7 Copyright © 1999 The Regents of the University of California3 Design Example (cont.)DGQGQYQRQWButton ⋅⋅⋅⋅= EQ QGQYQRQW ⋅⋅⋅⋅+DYButton QGQYQRQW ⋅⋅⋅⋅= EQ QGQYQRQW ⋅⋅⋅⋅+ DRQGQYQRQWEQ QRQWQYEQ QYQRQW⋅⋅⋅+⋅⋅ ⋅+⋅⋅[] ⋅=DWQGQYQREQ QW⊕() ⋅⋅=Consider alternative state diagrams and block diagrams – finalsimplest choice: number of FSMs, building blocks, Mealey/Moorethat meets
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