1Spring 2002 EECS150 - Lec13-seq3 version 2 Page 1EECS150 - Digital DesignLecture 17 - Sequential Circuits 3(Counters)March 19&21, 2002John WawrzynekSpring 2002 EECS150 - Lec13-seq3 version 2 Page 2Counters• Special sequential circuits (FSMs) that sequence though aset outputs.• Examples:– binary counter: 000, 001, 010, 011, 100, 101, 110, 111, 000, 001, …– gray code counter:000, 010, 110, 100, 101, 111, 011, 001, 000, 010, 110, …– one-hot counter: 0001, 0010, 0100, 1000, 0001, 0010, …– BCD counter: 0000, 0001, 0010, …, 1001, 0000, 0001– pseudo-random sequence generators: 10, 01, 00, 11, 10, 01, 00, ...• Moore machines with “ring” structure to STD:S3S0S2S1Spring 2002 EECS150 - Lec13-seq3 version 2 Page 3What are they used?• Examples from this semester:– Clock divider for UART circuit– UART control (count to 8 between bit capture).– Bit-serial multiplier control circuitry (from HW and quiz)– In general: counters simplify controller design by• providing a specific number of cycles of action,• sometimes used in with a decoder to generate a sequence of controlsignals.÷6416MHzSpring 2002 EECS150 - Lec13-seq3 version 2 Page 4Controller using Counters• Bit-serial multiplier:• Control Algorithm:FAA registerB registerHI register LOW registershiftBshiftAshiftHI shiftLOWcarrysumresetD-FF01selectSumrepeat n cycles { // outer (i) looprepeat n cycles{ // inner (j) loopshiftA, selectSum, shiftHI}shiftB, shiftHI, shiftLOW, reset}Note: The occurrence of a controlsignal x means x=1. The absenceof x means x=0.Spring 2002 EECS150 - Lec13-seq3 version 2 Page 5Controller using Counters• State Transition Diagram:– Assume presence of twocounters. An “i” counter for theouter loop and “j” counter forinner loop.counterCLK RSTCE TCIDLECEi,CEjRSTiCEi,CEjINNER<inner contol>CEi,CEjRSTjOUTER<outer contol>STARTSTARTTCiTCjTCiTCjTC is assured with the counterreaches it maximum count value.CE is “clock enable”. The counterincrements its value on the risingedge of the clock if CE is asserted.Spring 2002 EECS150 - Lec13-seq3 version 2 Page 6Controller using Counters• Controller circuitimplementation:• Outputs:CEi = q2CEj = q1RSTi = q0RSTj = q2shiftA = q1shiftB = q2shiftLOW = q2shiftHI = q1 + q2reset = q2selectSUM = q1IDLES RINNERS ROUTERS RSTARTTCiTCjcresetq0q1q22Spring 2002 EECS150 - Lec13-seq3 version 2 Page 7How do we design counters?• For binary counters (most common case) incremented circuit wouldwork:• In Verilog, a counter is specified as: x = x+1;– This does not imply an adder– An incrementer is simpler than an adder– And a counter is simpler yet.• In general, the best way to understand counter design is to think ofthem as FSMs, and follow general procedure. But before that ...register+1Spring 2002 EECS150 - Lec13-seq3 version 2 Page 8“Ripple” countersA3 A2 A1 A00000000100100011010001010110011110001001101010111100110111101111time• Each stage is ÷2 ofprevious.• Look at outputwaveforms:• Often called“asynchronous”counters.CLKA0A1A2A3Spring 2002 EECS150 - Lec13-seq3 version 2 Page 9Synchronous Counters• Binary Counter Design:Start with 3-bit version andgeneralize:a b ca+b+c+c b a c+ b+ a+0 0 0 0 0 10 0 1 0 1 00 1 0 0 1 10 1 1 1 0 01 0 0 1 0 11 0 1 1 1 01 1 0 1 1 11 1 1 0 0 0a+ = a’b+ = a ⊕ b cba 00 01 11 10 0 0 0 1 1 1 0 1 0 1c+ = a’c + abc’ + b’c = c(a’+b’) + c’(ab) = c(ab)’ + c’(ab) = c ⊕ abSpring 2002 EECS150 - Lec13-seq3 version 2 Page 10Synchronous Counters• How do we extend to n-bits?• Extrapolate c+: d+ = d ⊕ abc, e+ = e ⊕ abcd• Has difficulty scaling (AND gate inputs grow with n)• CE is “count enable”, allows external control of counting,• TC is “terminal count”, is asserted on highest value, allowscascading, external sensing of occurrence of max value.abca+b+c+dd+bb+cc+aa+dd+CETCSpring 2002 EECS150 - Lec13-seq3 version 2 Page 11Synchronous Countersbb+cc+aa+dd+CETC• How does this one scale?L Delay grows α n• Generation of TC signals very similar togeneration of carry signals in adder.• “Parallel Prefix” circuit reduces delay:a b c d e f g hTCa TCb TCc TCc TCd TCe TCf TCglog2nlog2nSpring 2002 EECS150 - Lec13-seq3 version 2 Page 12Binary Counter from JK FFs3Spring 2002 EECS150 - Lec13-seq3 version 2 Page 13Up-Down Counterc b a c+ b+ a+0 0 0 1 1 10 0 1 0 0 00 1 0 0 0 10 1 1 0 1 01 0 0 0 1 11 0 1 1 0 01 1 0 1 0 11 1 1 1 1 0Down-countSpring 2002 EECS150 - Lec13-seq3 version 2 Page 14With Parallel LoadSpring 2002 EECS150 - Lec13-seq3 version 2 Page 15Odd Counts• Extra combinational logic can beadded to terminate count beforemax value is reached:• Example: count to 12• Alternative:4-bit binarycounter= 11 ?reset= 11 ?4-bit binarycounterload4TCSpring 2002 EECS150 - Lec13-seq3 version 2 Page 16Ring Counters• “one-hot” counters0001, 0010, 0100, 1000, 0001, …“Self-starting” version:• What are these good for?DQDQDQDQq3q2q1q0D Q D Q D Q D Qq3q2q1S RS R S R S Rq0 0 0 0 0resetSpring 2002 EECS150 - Lec13-seq3 version 2 Page 17Ring CountersSpring 2002 EECS150 - Lec13-seq3 version 2 Page 18Johnson Counter4Spring 2002 EECS150 - Lec13-seq3 version 2 Page 19Register Summary• All register (this semester)based on Flip-flops:• Load-enable is a popular option:D Q D Q D Q D Qq3q2q1S RS R S R S Rq0 0 0 0 0resetd3d2d1d0DQDQDQDQq3q2q1S RS R S R S Rq0 0 0 0 0resetd301d201d101d001loadXilinx flip-flops employ a clockenable (CE) for same purpose.Spring 2002 EECS150 - Lec13-seq3 version 2 Page 20Shift-registers• Parallel load shift register:• “Parallel-to-serial converter”• Also, works as “Serial-to-parallel converter”, if q values areconnected out.• Also get used as controllers (ala “ring counters”)Spring 2002 EECS150 - Lec13-seq3 version 2 Page 21Universal
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