Expert Verilog, SystemVerilog & Synthesis TrainingSimulation and Synthesis Techniques for AsynchronousFIFO Design with Asynchronous Pointer ComparisonsClifford E. Cummings Peter AlfkeSunburst Design, Inc. Xilinx, Inc.ABSTRACTAn interesting technique for doing FIFO design is to perform asynchronous comparisons between the FIFO writeand read pointers that are generated in clock domains that are asynchronous to each other. The asynchronous FIFOpointer comparison technique uses fewer synchronization flip-flops to build the FIFO. The asynchronous FIFOcomparison method requires additional techniques to correctly synthesize and analyze the design, which are detailedin this paper.To increase the speed of the FIFO, this design uses combined binary/Gray counters that take advantage of the built-in binary ripple carry logic.The fully coded, synthesized and analyzed RTL Verilog model (FIFO Style #2) is included.This FIFO design paper builds on information already presented in another FIFO design paper where the FIFOpointers are synchronized into the opposite clock domain before running "FIFO full" or "FIFO empty" tests. Thereader may benefit from first reviewing the FIFO Style #1 method before proceeding to this FIFO Style #2 method.Post-SNUG Editorial Comment (by Cliff Cummings)Although this paper was voted “Best Paper - 1st Place” by SNUG attendees, this paper builds off of a second FIFOpaper listed as reference [1]. The first FIFO paper laid the foundation for some of the content of this paper;therefore, it is highly recommended that readers download and read the FIFO1 paper[1] to acquire backgroundinformation already assumed to be known by the reader of this paper.SNUG-2002San Jose, CAVoted Best Paper1st PlaceSNUG San Jose 2002 Simulation and Synthesis Techniques for AsynchronousRev 1.2 FIFO Design with Asynchronous Pointer Comparisons21.0 IntroductionAn asynchronous FIFO refers to a FIFO design where data values are written sequentially into a FIFO buffer usingone clock domain, and the data values are sequentially read from the same FIFO buffer using another clock domain,where the two clock domains are asynchronous to each other.One common technique for designing an asynchronous FIFO is to use Gray[4] code pointers that are synchronizedinto the opposite clock domain before generating synchronous FIFO full or empty status signals[1]. An interestingand different approach to FIFO full and empty generation is to do an asynchronous comparison of the pointers andthen asynchronously set the full or empty status bits[6].This paper discusses the FIFO design style with asynchronous pointer comparison and asynchronous full and emptygeneration. Important details relating to this style of asynchronous FIFO design are included. The FIFO styleimplemented in this paper uses efficient Gray code counters, whose implementation is described in the next section.2.0 Gray code counter - style #2One Gray code counter style uses a single set of flip-flops as the Gray code register with accompanying Gray-to-binary conversion, binary increment, and binary-to-Gray conversion[1].A second Gray code counter style, the one described in this paper, uses two sets of registers, one a binary counterand a second to capture a binary-to-Gray converted value. The intent of this Gray code counter style #2 is to utilizethe binary carry structure, simplify the Gray-to-binary conversion; reduce combinational logic, and increase theupper frequency limit of the Gray code counter.The binary counter conditionally increments the binary value, which is passed to both the inputs of the binarycounter as the next-binary-count value, and is also passed to the simple binary-to-Gray conversion logic, consistingof one 2-input XOR gate per bit position. The converted binary value is the next Gray-count value and drives theGray code register inputs.Figure 1 shows the block diagram for an n-bit Gray code counter (style #2).Figure 1 - Dual n-bit Gray code counter style #2SNUG San Jose 2002 Simulation and Synthesis Techniques for AsynchronousRev 1.2 FIFO Design with Asynchronous Pointer Comparisons3This implementation requires twice the number of flip-flops, but reduces the combinatorial logic and can operate ata higher frequency. In FPGA designs, availability of extra flip-flops is rarely a problem since FPGAs typicallycontain far more flip-flops than any design will ever use. In FPGA designs, reducing the amount of combinationallogic frequently translates into significant improvements in speed.The ptr output of the block diagram in Figure 1 is an n-bit Gray code pointer.Note: since the MSB of a binary sequence is equal to the MSB of a Gray code sequence, this design can be furthersimplified by using the binary MSB-flip-flop as the Gray code MSB-flip-flop. The Verilog code in this paper didnot implement this additional optimization. This would save one flip-flop per pointer.3.0 Full & empty detectionAs with any FIFO design, correct implementation of full and empty is the most difficult part of the design.There are two problems with the generation of full and empty:First, both full and empty are indicated by the fact that the read and write pointers are identical. Therefore,something else has to distinguish between full and empty. One known solution to this problem appends an extra bitto both pointers and then compares the extra bit for equality (for FIFO empty) or inequality (for FIFO full), alongwith equality of the other read and write pointer bits[1].Another solution, the one described in this paper, divides the address space into four quadrants and decodes the twoMSBs of the two counters to determine whether the FIFO was going full or going empty at the time the two pointersbecame equal.Figure 2 - FIFO is going full because the wptr trails the rptr by one quadrantIf the write pointer is one quadrant behind the read pointer, this indicates a "possibly going full" situation as shownin Figure 2. When this condition occurs, the direction latch of Figure 4 is set.SNUG San Jose 2002 Simulation and Synthesis Techniques for AsynchronousRev 1.2 FIFO Design with Asynchronous Pointer Comparisons4Figure 3 - FIFO is going empty because the rptr trails the wptr by one quadrantIf the write pointer is one quadrant ahead of the read pointer, this indicates a "possibly going empty" situation asshown in Figure 3. When this condition occurs, the direction latch of Figure 4 is cleared.Figure 4 - FIFO direction quadrant detection circuitryWhen the FIFO is
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