OPENLOCK S2’ T0OPENLOCKOPENLOCK1 Objectives2 Prelab3 High-level Specification4 Low-level specification5 Buses6 Forcing Internal Signals7 Clocks8 Command and Log Files9 Naming10 CheckoffsUniversity of California at BerkeleyCollege of EngineeringDepartment of Electrical Engineering and Computer ScienceEECS 150 Original Lab By: J.Wawrzynek and N. WeaverFall 2000 Later revisions by R. Fearing, and J. ShihXilinx Foundation 1.5 version: T. SmilksteinLab 2Finite State Machine1 ObjectivesYou will enter and debug a Finite State Machine (FSM). Using our definition of the problem and logic equations specifying the FSM’s operation, you will enter your design in the schematic editor and simulate it with the logic simulator.2 Prelab- Get a partner from your lab section!- Complete your IN1 (INput 1) and IN2 (INput 2) blocks- Write a .cmd (command) file to test your CLB (Combinational Logic Block).- Write one single .cmd file with all the FSM test scenarios specified in the check-off sheet.- Do as much as possible before your scheduled lab time. There is much to do in this lab. Some can be done on paper; the remainder can be done on the computers outside of lab time.3 High-level SpecificationYou are building the controller for a 2-bit serial lock used to control entry to a locked room. The lock has a RESET button, an ENTER button, and two two-position switches, CODE1 and CODE0, for entering the combination. For example, if the combination is 01-11, someone opening the lock would first set the two switches to 01 (CODE1 = low, CODE0 = high) and press ENTER. Then s/he would set the two switches to 11 (CODE1 = high, CODE0 = high) and press ENTER. This would cause the circuit to assert the OPEN signal, causing an electromechanical relay to be released and allowing the door to open. Our lock is insecure with only sixteen different combinations; think about how it might be extended.If the person trying to open the lock makes a mistake entering the switch combination, s/he can restart the process by pressing RESET. If s/he enters a wrong sequence, the circuitry would assert the ERROR signal, illuminating an error light. S/he must press RESET to start the process over. In this lab, you will enter a design for the lock’s controller in a new Xilinx project. Name this lab “lab2”. Make RESET and ENTER inputs. Simulate by pressing the ENTER button by forcing it high for aclock cycle. Use a two-bit wide input bus called CODE[1:0] for the two switches. (Information on how to use buses will be given later in this handout). The outputs are an OPEN signal and an ERROR signal.Figure 1 shows a decomposition of the combination lock controller, whose inputs and outputs are:Input Signal DescriptionRESET Clear any entered numbersENTER Read the switches (enter a number in the combination)CODE[1:0] Two binary switchesOutput signal DescriptionOPEN Lock opensERROR Incorrect combinationFigure 1: Controller for the combination LockFigure 2: State Transition Diagram4 Low-level specification 4.1 IN1 (INput 1) and IN2 (INput 2)Blocks IN1 and IN2 process the input signals COM1 (COMpare 1) and COM2 (COMpare 2) intoa simpler form for the FSM. Specifically, COM1 is asserted when CODE[1:0] is the combination’s first number. Similarly, COM2 is asserted for the second number. Partitioning the circuit in this way makes the combination easy to change.Choose your own combination; the two numbers must be different.This should be a simple block. Use a few AND gates and inverters.OPENLOCK4.2 MYCLBThe MYCLB (MY Combinational Logic Block) block takes RESET, ENTER, COM1, COM2, and present state and generates OPENLOCK and ERROR, as well as the next state. Figure 2 shows the state transition diagram, a Mealy machine since the transitions are labeled with both inputs and outputs. The white circle denotes the rest state (i.e., the state the machine starts in).By writing an “AND” term describing each row where an output is 1 and ORing these together, it’s easy to obtain a set of equations implementing the table shown in Figure 3.Translating a state transition diagram to a truth table is mechanical: Write a row for each transition. In Figure 4a, I’ve collapsed a few rows together by noting that when RESET is 1, the outputs and next state are the same for all states. Note RESET’ means NOT RESET.Implementing the equations of Figure 4a as written would be inefficient, so we introduce intermediate variables T0, ..., T6 as shown in Figure 4b. Make symbol and schematic for MYCLB using the equations in Figure 4b.OPENLOCKOPENLOCK=OPENLOCK S2’ T0=4.3 MYDFF(MY D Flip-Flops)Create a block called MYDFF that contains three D flip-flops (one for each state bit) with an asynchronous clear hooked to a pin called FFRESET (Flip-Flop RESET). The flip-flops you should use are the FDC (D Flip-flop with asynchronous Clear) flip-flops. Externally, connect FFRESET to 0 (i.e., not resetting), but during simulation you can force this to 1 to reset every flip-flop.5 Buses Buses are supported by the Xilinx software. Buses are collections of wires drawn as one by clicking on the “Draw Buses” icon and drawing as if you were drawing a wire. As with wires, to end a bus you click on the right mouse button and select a method to end the bus.You have a choice of “Add Bus Terminal”, “Add Bus Label”, or “Add Bus End”. “Add Bus Terminal” is how you want to end buses that will be connected to a symbol’s pins (inputs and outputs) when drawing a symbol’s schematic (reviewing how input and output wires were drawn in symbols in lab 1 may help make this easier to understand). Remember to specify whether the terminal is an input or output terminal. Also you will be required to input a name and how many wires the bus is made up of. It doesn’t matter whether you set the range from, say, for an eight-bit bus, 7 to 0, or from0 to 7, but it is necessary to be consistent in your all of your labeling. In labs where you’re using a TA schematic, it will usually be necessary to use 7 to 0. For this lab we will not use complex buses but they may be useful to you when doing later labs and when doing the project. Complex buses allow you to combine multiple buses and single wires into one bus. “Add Bus Label” is how to end all other buses. As you did when adding a terminal to a bus, you will need to specify a name and range when adding a bus label. “Add Bus End” ends the bus without naming it. To name the bus later, edit an existing label, or
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