1Fall 2002 EECS150 - Lec13-cla3Page 1EECS150 - Digital DesignLecture 13 - Combinational Logic & Arithmetic Circuits Part 3October 8, 2002John WawrzynekFall 2002 EECS150 - Lec13-cla3Page 2Multiplicationa3a2a1a0Multiplicandb3b2b1b0MultiplierXa3b0a2b0a1b0a0b0a3b1a2b1a1b1a0b1Partiala3b2a2b2a1b2a0b2productsa3b3a2b3a1b3a0b3 . . . a1b0+a0b1a0b0ProductMany different circuits exist for multiplication.Each one has a different balance between speed (performance) and amount of logic (cost).2Fall 2002 EECS150 - Lec13-cla3Page 3“Shift and Add” Multiplier• Sums each partial product, one at a time.• In binary, each partial product is shifted versions of A or 0.Control Algorithm:1. P ← 0, A ← multiplicand, B ← multiplier2. If LSB of B==1 then add A to Pelse add 03. Shift [P][B] right 14. Repeat steps 2 and 3 n-1 times.5. [P][B] has product.Bn-bit shift registersPAn-bit register+010 n-bit adder•Cost α n, Τ = n clock cycles.• What is the critical path for determining the min clock period?Fall 2002 EECS150 - Lec13-cla3Page 4“Shift and Add” MultiplierSigned Multiplication:Remember for 2’s complement numbers MSB has negative weight:ex: -6 = 110102= 0•20+ 1•21+ 0•22+ 1•23-1•24= 0 + 2 + 0 + 8 - 16 = -6• Therefore for multiplication:a) subtract final partial productb) sign-extend partial products• Modifications to shift & add circuit:a) adder/subtractorb) sign-extender on P shifter register 112022−−−=−=∑nniNiixxX3Fall 2002 EECS150 - Lec13-cla3Page 5Array Multiplierb3 0 b2 0 b1 0 b0 0P7 P6 P5 P4a00a10a20a30P0P1P2P3FAbjsum insum outcarryoutaicarryinEach row: n-bit adder with AND gatesWhat is the critical path?Generates all n partial products simultaneously.Fall 2002 EECS150 - Lec13-cla3Page 6Carry-save Addition• Speeding up multiplication is a matter of speeding up the summing of the partial products.• “Carry-save” addition can help.• Carry-save addition passes (saves) the carries to the output, rather than propagating them.• Example: sum three numbers,310= 0011, 210= 0010, 310= 00113100011+ 2100010c 0100 = 410s 0001 = 1103100011c 0010 = 210s 0110 = 6101000 = 810carry-save addcarry-save addcarry-propagate add• In general, carry-save addition takes in 3 numbers and produces 2.• Whereas, carry-propagate takes 2 and produces 1.• With this technique, we can avoid carry propagation until final addition4Fall 2002 EECS150 - Lec13-cla3Page 7Carry-save Circuits• When adding sets of numbers, carry-save can be used on all but the final sum.• Standard adder (carry propagate) is used for final sum.FAFAFA FAFA FA FA FA0CSAs cs cs cs cs cs cs cs ccCSACPACSACSAx0x1x2Fall 2002 EECS150 - Lec13-cla3Page 8Array Multiplier using Carry-save Additionb3 0 b2 0 b1 0 b0 0P7 P6 P5 P4a00a1a2a3P0P1P2P310000000000FAbjsum insum outcarryoutaicarryinFast carry-propagate adder5Fall 2002 EECS150 - Lec13-cla3Page 9Carry-save AdditionCSA is associative and communitive. For example:(((X0 + X1)+X2 )+X3 ) = ((X0 + X1)+(X2 +X3 ))• A balanced tree can be used to reduce the logic delay.• This structure is the basis of the Wallace Tree Multiplier.• Partial products are summed with the CSA tree. Fast CPA (ex: CLA) is used for final sum.• Multiplier delay α log3/2N + log2NCSACPACSACSAx0x1x2CSACSACSAx3x4x5x6x7log3/2Nlog2NFall 2002 EECS150 - Lec13-cla3Page 10Division1001 QuotientDivisor 1000 1001010 Dividend–1000101011010–100010 Remainder (or Modulo result)• See how big a number can be subtracted, creating quotient bit on each stepBinary ⇒ 1 * divisor or 0 * divisor• Dividend = Quotient x Divisor + Remaindersizeof(dividend) = sizeof(quotient) + sizeof(divisor)• 3 versions of divide, successive refinement6Fall 2002 EECS150 - Lec13-cla3Page 11DIVIDE HARDWARE Version 1• 64-bit Divisor register, 64-bit adder/subtractor, 64-bit Remainder register, 32-bit Quotient registerRemainderQuotientDivisoradd/subShift RightShift LeftWriteControl32 bits64 bits64 bitsFall 2002 EECS150 - Lec13-cla3Page 122b. Restore the original value by adding the Divisor register to the Remainder register, &place the sum in the Remainder register. Alsoshift the Quotient register to the left, setting the new least significant bit to 0.Divide Algorithm Version 1Takes n+1 steps for n-bit Quotient & Rem.Remainder Quotient Divisor00000111 0000 00100000710210Test RemainderRemainder < 0Remainder≥ 01. Subtract the Divisor register from the Remainder register, and place the result in the Remainder register.2a. Shift the Quotient register to the left setting the new rightmostbit to 1.3. Shift the Divisor register right 1 bit.DoneYes: n+1 repetitions (n = 4 here)Start: Place Dividend in Remaindern+1repetition?No: < n+1 repetitions7Fall 2002 EECS150 - Lec13-cla3Page 13Version 1 Division Example 7/2Iteration step quotient divisor remainder0 Initial values 0000 0010 0000 0000 01111 1: rem=rem-div 0000 0010 0000 1110 01112b: rem<0 ⇒ +div, sll Q, Q0=0 0000 0010 0000 0000 01113: shift div right 0000 0001 0000 0000 01112 1: rem=rem-div 0000 0001 0000 1111 01112b: rem<0 ⇒ +div, sll Q, Q0=0 0000 0001 0000 0000 01113: shift div right 0000 0000 1000 0000 01113 1: rem=rem-div 0000 0000 1000 1111 11112b: rem<0 ⇒ +div, sll Q, Q0=0 0000 0000 1000 0000 01113: shift div right 0000 0000 0100 0000 01114 1: rem=rem-div 0000 0000 0100 0000 00112a: rem≥0 ⇒ sll Q, Q0=1 0000 0000 0100 0000 00113: shift div right 0000 0000 0010 0000 00115 1: rem=rem-div 0000 0000 0010 0000 00012a: rem≥0 ⇒ sll Q, Q0=1 0001 0000 0010 0000 00013: shift div right 0001 0000 0001 0000 0001Fall 2002 EECS150 - Lec13-cla3Page 14Observations on Divide Version 1• 1/2 bits in divisor always 0⇒ 1/2 of 64-bit adder is wasted⇒ 1/2 of divisor is wasted• Instead of shifting divisor to right, shift remainder to left?•1ststep cannot produce a 1 in quotient bit (otherwise too big)⇒ switch order to shift first and then subtract, can save 1 iteration8Fall 2002 EECS150 - Lec13-cla3Page 15DIVIDE HARDWARE Version 2•32-bit Divisor register, 32-bit ALU, 64-bit Remainder register, 32-bit Quotient registerRemainderQuotientDivisoradd/subShift LeftWriteControl32 bits32 bits64 bitsShift LeftFall 2002 EECS150 - Lec13-cla3Page 16Divide Algorithm Version 2Remainder Quotient Divisor00000111 0000 00107102103b. Restore the original value by adding the Divisor register to the left half of
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