EECS 150 Components and Design Techniques for Digital Systems Lec 24 Sequential Logic Revisited David Culler Electrical Engineering and Computer Sciences University of California Berkeley http www eecs berkeley edu culler http www inst eecs berkeley edu cs150 Traversing Digital Design EECS150 wks 6 15 Sequential Circuit Design and Timing EECS150 wks 1 6 EE 40 CS61C Types of Latches We have focused on D flips D latch D FlipFlop Registers ld clr Most commonly used today CMOS FPGA Many other types of latches RS JK T Should be familiar with these too Opportunity to look much more closely at timing behavior Latch vs Flip Flops Timing Methodology Recall Forms of Sequential Logic Asynchronous sequential logic state changes occur whenever state inputs change elements may be simple wires or delay elements Synchronous sequential logic state changes occur in lock step across all storage elements using a periodic waveform the clock Clock Example ring oscillator B A C D E Period of Repeating Waveform tp Gate Delay td A X 0 B 1 C 0 D 1 E 0 1 b Timing waveform X Recall General Model of Synchronous Circuit c lo c k in p u t in p u t CL re g CL o u tp u t re g o p tio n fe e d b a c k o u tp u t Our methodology so far registers as D flipflops with common control Single phase clock edge triggered design Tsu Th input clock Assumptions underlying the clean abstraction Input to FF valid a setup time before clock edge Outputs don t change too quickly after clock edge hold time Clk to Q hold time Circuits with Feedback How to control feedback What stops values from cycling around endlessly X1 X2 Xn switching network Z1 Z2 Zn Simplest Circuits with Feedback Two inverters form a static memory cell Will hold value as long as it has power applied 1 stored value 0 How to get a new value into the memory cell Selectively break feedback path Load new value into cell remember data load stored value Latches D Q Level sensitive latch a holds value when clock is low Transparent when clock is high What does it take to build a consistent timing methodology with only latches Very hard All stages transparent at same time Require that minimum propagation delay is greater than high phase of the clock duty period D in clk a b Q b D Q Clocks Used to keep time Wait long enough for inputs R and S to settle Then allow to have effect on value stored Clocks are regular periodic signals Period time between ticks Duty cycle time clock is high between ticks expressed as of period duty cycle in this case 50 period Two phase non overlapping clocks Sequential elements partition into two classes phase0 ele ts feed phase1 phase1 ele ts feed phase0 Approximate single phase each register replaced by a pair of latches on two phases Can push logic across retiming Can always slow down the clocks to meet all timing constraints a D Q clk 0 in clk0 clk1 a b b c l D Q clk1 Master Slave Structure D c lk Q s e t u p tim e c lo c k t o Q d e la y clk clk clk Construct D flipflop from two D latches clk clk clk clk clk Latches vs FlipFlips Level sensitive vs edge triggered Very different design methodologies for correct use Both are clocked but latch is asynchronous Output can change while clock is high D Clk Q Q FF Latch Asynchronous R S Latch Cross coupled NOR gates Similar to inverter pair with capability to force output to 0 reset 1 or 1 set 1 R 1 0 Q Q R S S 0 1 Q Cross coupled NAND gates Similar to inverter pair with capability to force output to 0 reset 0 or 1 set 0 S R Q S R Q Q State Behavior of R S latch characteristic equation Q t S R Q t Transition Table S t 0 0 0 0 1 1 1 1 R t 0 0 1 1 0 0 1 1 Q t 0 1 0 1 0 1 0 1 Q t 0 hold 1 0 reset 0 1 set 1 X not allowed X R Q S Q S Q t 0 0 X 1 1 0 X 1 R Sequential output depends on history when inputs R 0 S 0 but asynchronous Theoretical R S Latch Behavior R S Q Q SR 10 SR 00 SR 01 SR 01 Q Q 0 1 SR 01 Q Q 1 0 SR 10 SR 11 State Diagram States possible values Transitions changes based on inputs SR 11 SR 01 possible oscillation between states 00 and 11 Q Q 0 0 SR 11 SR 00 SR 11 SR 00 SR 10 Q Q 1 1 SR 00 SR 10 Timing Behavior Reset R S Q Q Hold R Q S Q Set Reset Set 100 Race Observed R S Latch Behavior Very difficult to observe R S latch in the 1 1 state One of R or S usually changes first Ambiguously returns to state 0 1 or 1 0 A so called race condition Or non deterministic transition SR 10 SR 00 SR 01 SR 01 Q Q 0 1 SR 01 Q Q 1 0 SR 00 SR 10 SR 10 SR 11 SR 11 SR 00 Q Q 0 0 SR 11 SR 00 Announcements Great early check offs About 2 3s of class signed up Excellent projects on Monday If you signed up and we didn t get to you check off at regular time but get 10 anyways using frozen files Issues on CP3 today is deadline to talk to us borrowed or provided solutions Engineer s code of ethics always state sources of work Credit where it is due protect yourself protect your employer EECS in the NEWS Towards quantum computing 5 7 bit devices have been built Fundamental algorithmic differences Factoring large prime numbers Computational view of quantum theory New undergrad course Kubiatowicz vazirani Gated R S Latch Control when R and S inputs matter Otherwise the slightest glitch on R or S while enable is low could cause R R Q enable change in value stored Ensure R S stable before utilized to avoid transient R 1 S 1 Set S R enable Q Q Q S S 100 Reset Towards a Synchronous Design Controlling an R S latch with a clock Can t let R and S change while clock is active allowing R and S to pass Only have half of clock period for signal changes to propagate Signals must be stable for the other half of clock period R R Q clock S Q S stablechanging stable changing stable R and S clock JK Flip Flops J t 0 0 0 0 1 1 1 1 K t 0 0 1 1 0 0 1 1 Q t 0 1 0 1 0 1 0 1 Q t 0 hold 1 0 reset …
View Full Document
Unlocking...