University of California at BerkeleyCollege of EngineeringDepartment of Electrical Engineering and Computer SciencesEECS150 J. WawrzynekSpring 2002Homework #2This homework is due on Friday Feb 8th by noon. Homework will be accepted in theEECS150 homework box outside 218 Cory Hall. Late homework will be penalized by50%. No late homework will be accepted after the solution is handed out.1. Flip-flops and timing.a) For the circuit shown, assume that all the flip-flops initially hold logic 0. Draw thewaveform that appears at point y.b) Assume the flip-flop setup time is 75ps and its clock-to-Q delay is 100ps. If the muxpropagation delay is 150ps, what is the maximum clock frequency for this circuit?QD QDQD10LDxyclkclkLDxy2. Logic gate timing waveforms.Below is shown the waveforms corresponding to a low-to-high and a high-to-lowtransition for an inverter. Draw approximate transition wavefoms for the other situationsshown below. Assume that all transistors in all the gates and inverters are of the samestrength.a) Vx initially is high, set a=b=high.b) Vx initially is low, set a=high, b=lowc) Vx initially is low, set a=b=low.VxtxVxtabxVxtabxVxtabxd) Show both transitions.3. Gate delay.Consider a CMOS AND gate constructed as a NAND gate followed by an inverter.Assume the inverter propagation delay is expressed as follows:fP⋅+= 10050τwhere f is the fanout of the inverter, expressed in number of transistor-gate inputs(inverters contribute 2 to f, one input of 2-input gates contribute 2,). Assume this inverterhas the same propagation delay for both low-to-high and high-to-low transistions.The NAND gate propagation delay is expressed as:ffPHLPLH⋅+=⋅+=12510075100ττFor the low-to-high and high-to-low transitions, respectively. Write expressions for thepropagation delay of the AND gate:==PHLPLHττVxtx4. Power/energy units.a) Consider a logic gate driving an output with an average of one transition per eightclock cycles (clock frequency is 100MHz). The output has a total capacitance of10fF, and Vdd=3volts. What is the average power consumption of the gate?b) Battery storage is often expressed in Watt-hours. What is the energy storage capacityin Joules of a 10 Watt-hour battery? How long would it power the above gate?5. Switching power.Consider the simple AND/OR circuit shown below. New values are applied to the fourinputs at a rate of f. Input values are applied as independent uniform random sequencesto each of the four inputs; i.e., for each input, on each appearance of a new input,Prob(1)=Prob(0)=1/2. Write an expression for the average power consumed by gate 1 interms of f and the switching energy Esw. Do the same for gate 3.1236. Power and voltage scaling.To first approximation, under a limited voltage range, a reduction is power supplyvoltage (Vdd) in MOS circuits results in a linear increase in gate delay and thusmaximum clock rate. This fact is often used to reduce power consumption in cases wherea reduction in performance can be tolerated, or compensated for in another way.Consider a special processor inside a car engine, whose job is to control the fuel airmixture to the injectors. Let’s assume that the processor must make 100 adjustments persecond and it takes 5K operations for each adjustment. Assume that we chose to use aprocessor that has peak performance of 1M operations/sec and at that rate uses 1Watt.Your boss tells you that 1 Watt is too much. Without changing the supply voltage, isthere a way to reduce the power consumption? If so, by how much? Is there a way toreduce the power consumption even more by lowering the supply voltage? If so, whatvoltage level would you use and what would be the resulting
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