Spring 2011EECS150 - Lec11-proj2Page EECS150 - Digital DesignLecture 11 - Project Description, Part 2: CPU Pipeline, Memory BlocksFeb 22, 2010John Wawrzynek1Spring 2011EECS150 - Lec11-proj2Page Project OverviewA. Serial InterfaceB. MIPS150 pipeline structureC. Memories, project memories and FPGAsD. Dynamic Memory (DRAM)E. CachesF. Video subsystemG. Ethernet InterfaceH. Project specification and grading standard2Spring 2011EECS150 - Lec11-proj2Page MIPS150 Pipeline3IXMThe blocks in the datapath with the greatest delay are: IMEM, ALU, and DMEM. Allocate one pipeline stage to each:Use PC register as address to IMEM and retrieve next instruction. Instruction gets stored in a pipeline register, also called “instruction register”, in this case.Most details you will need to work out for yourself. Some details to follow ... In particular, let’s look at hazards.Access data memory or I/O device for load or store. Allow for setup time for register file write.Use ALU to compute result, memory address, or compare registers for branch. Control Hazard ExampleSpring 2011EECS150 - Lec11-proj2Page MIPS 3-stage Pipeline4 beq $1, $2, L1IXM add $5, $3, $4IXML1: sub $7, $6, $5IXMIXbranch address ready but needed here!Architected branch delay slot allows us to delay branch target capture to here.Therefore no extra logic is required. delay slotadd $5, $3, $4L1: sub $7, $6, $5Spring 2011EECS150 - Lec11-proj2Page MIPS 3-stage Pipeline5 lw $5, offset($4)IXMIXMIXMMemory value known here. It is written into the regfile on this edge.value needed here!Load Hazard add $7, $6, $5 add $10, $9, $8“Architected load delay slot” on MIPS allows compiler to deal with the delay. No regfile bypassing needed here assuming regfile “write before read”. add $7, $6, $5 add $10, $9, $8Spring 2011EECS150 - Lec11-proj2Page MIPS 3-stage Pipeline6 add $5, $3, $4IXM add $7, $6, $5IXMreg 5 value updated herereg 5 value needed here!Data Hazard1. Stall the pipeline behind first add to wait for result to appear in register file. NOT ALLOWED this semester.2. Selectively forward ALU result back to input of ALU.Ways to fix:• Need to add mux at input to ALU, add control logic to sense when to activate. A bit complex to design. Check book for details.Spring 2011EECS150 - Lec11-proj2Page Project CPU Pipelining Summary• Pipeline rules: – Writes/reads to/from DMem use leading edge of “M”– Writes to RegFile use trailing edge of “M”– Instruction Decode and Register File access is up to you.• 1 Load Delay Slot, 1 Branch Delay Slot– No Stalling may be used to accommodate pipeline hazards (in final version).• Other:– Target frequency to be announced later (50-100MHz)– Minimize cost– Posedge clocking only7IXMinstruction fetchexecute access data memory3-stage pipelineSpring 2011EECS150 - Lec11-proj2Page Memory-Block Basics• Uses:Whenever a large collection of state elements is required. – data & program storage – general purpose registers – data buffering – table lookups – CL implementation • Basic Types:– RAM - random access memory – ROM - read only memory – EPROM, FLASH - electrically programmable read only memory 8M X N memory:Depth = M, Width = N.M words of memory, each word N bits wide.log2(M)Spring 2011EECS150 - Lec11-proj2Page Memory Components Types:• Volatile:– Random Access Memory (RAM): • DRAM "dynamic" • SRAM "static" • Non-volatile:– Read Only Memory (ROM): • Mask ROM "mask programmable" • EPROM "electrically programmable" • EEPROM "erasable electrically programmable" • FLASH memory - similar to EEPROM with programmer integrated on chip9Focus TodayAll these types are available as stand alone chips or as blocks in other chips.Focus MondaySpring 2011EECS150 - Lec11-proj2Page Standard Internal Memory Organization • RAM/ROM naming convention: – examples: 32 X 8, "32 by 8" => 32 8-bit words – 1M X 1, "1 meg by 1" => 1M 1-bit words 2-D arrary of bit cells. Each cell stores one bit of data.10Special circuit tricks are used for the cell array to improve storage density.Spring 2011EECS150 - Lec11-proj2Page Address Decoding•The function of the address decoder is to generate a one-hot code word from the address.•The output is use for row selection.•Many different circuits exist for this function. A simple one is shown to the right.11Addresssel_row1sel_row2Spring 2011EECS150 - Lec11-proj2Page Memory Block InternalsThese circuits are just functional abstractions of the actual circuits used. 12sel_row1sel_row2For read operation, functionally the memory is equivalent to a 2-D array off flip-flops with tristate outputs on each:For write operation, functionally equivalent includes a means to change state value:Spring 2011EECS150 - Lec11-proj2Page SRAM Cell Array Details13Most common is 6-transistor (6T) cell array.worbit bit worbit bit worbit bit worbit bit worbit bit worbit bit word line bit bitWord selects this cell, and all others in a row.For write operation, column bit lines are driven differentially (0 on one, 1 on the other).Values overwrites cell state.For read operation, column bit lines are equalized (set to same voltage), then released. Cell pulls down one bit line or the other.Spring 2011EECS150 - Lec11-proj2Page Column MUX in ROMs and RAMs: • Permits input/output data widths different from row width.• Controls physical aspect ratio – Important for physical layout and to control delay on wires.14Technique illustrated for read operation. Similar approach for write.Spring 2011EECS150 - Lec11-proj2Page Cascading Memory-Blocks15How to make larger memory blocks out of smaller ones.Increasing the width. Example: given 1Kx8, want 1Kx16Spring 2011EECS150 - Lec11-proj2Page Cascading Memory-Blocks16How to make larger memory blocks out of smaller ones.Increasing the depth. Example: given 1Kx8, want 2Kx8Spring 2011EECS150 - Lec11-proj2Page Multi-ported Memory• Motivation:– Consider CPU core register file:• 1 read or write per cycle limits processor performance.• Complicates pipelining. Difficult for different instructions to simultaneously read or write regfile.• Common arrangement in pipelined CPUs is 2 read ports and 1 write port.databufferdisk or network interfaceCPU–I/O data buffering: 17AaDinaWEaAbDinbWEbDual-portMemoryDoutaDoutb•dual-porting allows both sides to simultaneously access memory at full bandwidth. Spring 2011EECS150 - Lec11-proj2Page
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