OverviewThe FIFO InterfaceThe Handshake and Data TransferAdvantages of the FIFO InterfaceWhen to use the FIFO InterfaceA Danger: RedCombinational LoopsEECS150: Interfaces: “FIFO” (a.k.a. Ready/Valid)UC Berkeley College of EngineeringDepartment of Electrical Engineering and Computer Science1 OverviewPerhaps the most important part of creating a large design is how well you connect the different piecesthat comprise the design. Specifically, you are concerned with how the outputs of one component connectto the inputs of another component.This document will discuss a general handshake-based interface (input/output port specification)that modules in your design can conform to. By following this interface specification, you will be able toconnect different modules with no complexity or combinational logic stuck in b e tween them. By followingthis interface specification, you will also avoid designing around your own timing assumptions of whendifferent comp onents need data. As the interface is handshake-based, modules will instead talk to oneanother with regards to when they need data.2 The FIFO InterfaceThis document’s interface specification, which we will the FIFO Interface1as it works especially wellwith units that pass data in a single direction, such as FIFOs, is shown in Figure1.Figure 1 The FIFO InterfaceValidReadyDataModule A(Source)Module B(Sink)In Figure 1, two modules (called the source and the sink) are connected to one another. When datais being passe d from module to module, the source is the module that is outputting data. The sink isthe module that is receiving that data.In addition to showing the source and the sink, Figure 1 also shows three signals between the two:Data, Valid, and Ready. Data is the wire that actually passes data from the s ource to the sink. Valid andReadyare known as handshaking signals which allow the source and the sink to communicate withregards to when it is time to pass the data.The Valid signal (output from the source and input to the sink) indicates that the source has putvalid data on the Data line this cycle. Validis what is called a state signal: it is high only when datais valid. If data is not valid on the Data line during a particular cycle, Valid should be low during thatcycle.The Ready signal (output from the sink and input to the source) indicates that the sink is ready toreceive new data. Ready can be asserted as soon as the sink is ready to rece ive new data. Whenever thesink is not ready to receive new data, Ready should be low.1The “FIFO Interface” is also known as the “Ready/Valid” interface due to the names of its handshake signals: Readyand Valid.13 The Handshake and Data TransferThe FIFO Interface handshake ensures that data passes from the source to the sink only when the sourcehas valid data to pass and when the sink is ready to receive that data. In other words, when Valid andReady are both high, data on Data will be latched into the sink on the next rising edge. This is animportant point: since EECS150 is concerned with synchronous design, data will only be transferred atthe rising edge. This handshake, and when it passes data, is shown in Figure 2.Figure 2 Data transfer at the rising edgeClockValidReadytransferThis transfer of data happens on every rising edge where Valid and Ready are both asserted. For eachrising edge, however, only one piece of data is transferred. For example, if Valid and Ready are both highfor two consecutive cycles, we transfer two data words (on consecutive clock cycles; see Figure 3).Note that data transfer only occurs when both Valid and Ready are high. For example, in Figure 4,neither Valid nor Ready are high. Thus, no data is transferred. Likewise in Figure 5 and Figure 6: ifonly one of the two handshaking signals is high, no data is transferred. Figure 7 shows another example:if the two handshaking signals are both high at some point, but are out of phase, no data is transferred.4 Advantages of the FIFO InterfaceThe FIFO Interface e liminates timing assumptions in your design and removes intermediate combina-tional logic between modules.Modules that interface with different pieces of hardware must follow the rules laid out by that hard-ware down to the cycle. To keep track of when every piece of data must be sent / every control signalmust be asserted, students will often construct external counters that count time to determine whendifferent events should happen. This type of design is crippled by the fact that students are makinglarge timing assumptions about when each of their modules requires data X or control signal Y. Eachmodule doesn??t give feedback on these counters: they are either right or wrong, but are not based onthe actual state of the module. If a counter gets misaligned, the circuit will fail horribly.By basing data transfer on handshaking, each module that is handling the data has input as to whenthe data should and can be passed along. After designing each module, you as the student can forgetabout the timing of that module, and trust that it will keep track of when it is done processing dataand when it is ready to receive more data. The second benefit of the FIFO interface is that it providesa 2-wire standard for connecting modules. To connect to modules that follow the FIFO interface, all2Figure 3 Two data transfers at two consecutive rising edgesClockValidReadytransfertransferFigure 4 Both handshaking s ignals are low: no data is transferredClockValidReadyFigure 5 Valid is high and Ready is low: no data is transferredClockValidReady3Figure 6 Valid is low and Ready is high: no data is transferredClockValidReadyFigure 7 Both handshaking signals are high at some point, but are out of phase: no data is transferredClockValidReadyyou have to do is connect the Data port from the source to the sink, the Valid port from the source tothe sink, and the Ready port from the sink to the source. When students don’t follow this standard,they typically substitute in large and complex messes of combinational logic in between each of theirmodules to connect them together. If you design by the FIFO interface, and internalize t helogic that generates Valid and Ready, when it comes time to connect modules, you can do soby just connecting ports together. Down the road of the project, this will save you many hoursof frustration.5 When to use the FIFO InterfaceThe FIFO Interface coordinates data transfer. Hence, whenever a module you w rite passes data toanother module, that
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