Teaching Staff Professor John Wawrzynek Warznek 631 Soda Hall johnw cs berkeley edu Office Hours Tu Th 2 3pm EECS150 Digital Design Lecture 1 Introduction January 18 2005 All TA office hours held in 125 Cory Check website for days and times John Wawrzynek Electrical Engineering and Computer Sciences University of California Berkeley http www inst eecs berkeley edu cs150 Greg Gieling Po kai Chen Head TA Spring 2005 EECS150 lec01 intro Spring 2005 Page 1 Outline EECS150 lec01 intro Page 2 If you are enrolled and plan to take the course you must attend your lab section next week if not you will be dropped from the class roster No exceptions If you are on the waitlist we have room for you however you must 1 Have taken the prerequisites CS61C EECS40 2 Attend lectures and do the homework the first two weeks 3 In the second week of classes go to the lab section in which you wish to enroll Give the TA your name and student ID If the lab section is full the TA will tell you if so you must find a different section 4 Later we will process the waitlist based on these requests and lab section openings 5 Note if you are not on the waitlist you will not be considered for enrollment EECS150 lec01 intro Alex Krasnov Enrollment Enrollment Attendance Course Materials Content Course Structure Grading A Few Basic Principles of Digital Design Spring 2005 Andrew Schultz Page 3 No lab or discussion sections this week Yes lab lecture Friday Spring 2005 EECS150 lec01 intro Page 4 1 Attendance Lab Lecture Attend regular lectures and ask questions Attend weekly lab lecture Friday Lab lecture will be webcast and recorded on the website Attend your lab section You must stick with the same lab section all semester Lab exercises will be done individually project with a partner We will put together a lab section exchange in a few weeks to help you move to a different section Attend any discussion section You may attend any discussion section that you want regardless of which one you are enrolled in The instructor and TAs hold regular office hours see class webpage Please take advantage of this opportunity Spring 2005 EECS150 lec01 intro Held in the lab 125 Cory so we can do demonstrations This is an important part of the course You get background and practical information regarding the lab exercises and project checkpoints Also we will have a mandatory short quiz at the beginning of each lab lecture we might move some of these to Thursday class Quiz will be based on one of the weekly homework problems Two quiz scores for each student will be dropped at the end of the semester so you can miss two quizzes save this option for important dates like job interview trips etc Telebears say Friday 1 2 Website says Friday 2 3 Which one is it Spring 2005 Page 5 Course Materials Textbook Katz Borriello EECS150 lec01 intro Page 6 Course Content Components and Design Techniques for Digital Systems more specifically Synchronous Digital Hardware Systems Other useful books on reserve in Eng Library Synchronous Clocked all changes in the system are controlled by a global clock and happen at the same time not asynchronous Digital All inputs outputs and internal values signals take on discrete values not analog Example digital representation music waveform Class notes homework lab assignments solutions and other documentation will be available on the class webpage http www inst eecs berkeley edu cs150 index html Check the class webpage and newsgroup often You are responsible for checking the class webpage at least once every 24 hours Spring 2005 EECS150 lec01 intro Page 7 A series of numbers is used to represent the waveform rather than a voltage or current as in analog systems Spring 2005 EECS150 lec01 intro Page 8 2 Course Content Course Content Hardware Architectures Arithmetic units controllers Programming Languages Asm Machine Lang CS 61C Memory elements logic gates busses Transistor level circuits Transistors wires Spring 2005 EECS150 lec01 intro Finite State Machines Timing Clocking Device Technology Implications FlipFlops Page 9 Controller Design Gates Arithmetic Units Encoding Framing Circuits EE 40 Testing Debugging Devices Hardware Architecture Transistor Physics Hardware Design Language HDL IC processing Spring 2005 Design Flow CAD EECS150 lec01 intro Page 10 Course Evolution Final project circa 1980 Final project circa 1995 Example project pong game with buttons for paddle and LEDs for output Few 10 s of logic gates Gates hand wired together on bread board protoboard No computer aided design tools Debugged with oscilloscope and logic analyzer EECS150 lec01 intro Synchronous Circuits HDL Course Evolution Spring 2005 Fundamentals of Boolean Logic Instruction Set Arch Machine Organization Not a course on transistor physics and transistor circuits Although we will look at these to better understand the primitive elements for digital circuits Not a course on computer architecture or the architecture of other systems Although we will look at these as examples Deep Digital Design Experience Page 11 Example project MIDI music synthesizer Few 1000 s of logic gates Gates wired together internally on field programmable gate array FPGA development board with some external components Circuit designed by hand computer aided design tools to help map the design to the hardware Debugged with circuit simulation oscilloscope and logic analyzer Spring 2005 EECS150 lec01 intro Page 12 3 Moore s Law 2x stuff per 1 2 yr Course Evolution Final project circa 2000 Spring 2005 EECS150 lec01 intro Page 13 Example project eTV streaming video broadcast over Ethernet student project decodes and displays video Few 10 000 s of logic gates Gates wired together internally on FPGA development board and communicate with standard external components Circuit designed with logic synthesis tools computer aided design tools to help map the design to the hardware Debugged with circuit simulation logic analyzer and in system debugging Spring 2005 EECS150 lec01 intro tools Course Evolution Course Evolution Final project it getting too complex Design mythology getting too high level Losing touch with fundamentals of logic design Our Plan Final project circa 2005 Example project Multi user networked Quake in hardware 10Million logic gates Circuit designed with logicsynthesis tools and library of high level blocks Debugged with in system debugging tools Emphasize fundamental design concepts deemphasize advanced techniques Stay with current development platform
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