1Spring 2005 EECS150 - Lec06-synthesisPage 1EECS150 - Digital DesignLecture 6 - SynthesisFebruary 3, 2005John WawrzynekSpring 2005 EECS150 - Lec06-synthesisPage 2Logic Synthesis • Verilog and VHDL started out as simulation languages, but quickly people wrote programs to automatically convert Verilog code into low-level circuit descriptions (netlists).• Synthesis converts Verilog (or other HDL) descriptions to implementation technology specific primitives:– For FPGAs: LUTs, flip-flops, and RAM blocks– For ASICs: standard cell gate and flip-flop libraries, and memory blocks.SynthesisToolVerilogHDLcircuitnetlistSpring 2005 EECS150 - Lec06-synthesisPage 3Why Logic Synthesis?1. Automatically manages many details of the design process: Fewer bugs Improved productivity2. Abstracts the design data (HDL description) from any particular implementation technology.– Designs can be re-synthesized targeting different chip technologies. Ex: first implement in FPGA then later in ASIC.3. In some cases, leads to a more optimal design than could be achieved by manual means (ex: logic optimization)Why Not Logic Synthesis?1. May lead to non-optimal designs in some cases.Spring 2005 EECS150 - Lec06-synthesisPage 4How does it work?• A variety of general and ad-hoc (special case) methods:– Instantiation: maintains a library of primitive modules (AND, OR, etc.) and user defined modules.– “macro expansion” / substitution: a large set of language operators (+, -, Boolean operators, etc.) and constructs (if-else, case) expand into special circuits.– Inference: special patterns are detected in the language description and treated specially (ex: inferring memory blocks from variable declaration and read/write statements, FSM detection and generation from “always @ (posedge clk)” blocks).– Logic optimization: Boolean operations are grouped and optimized with logic minimization techniques.– Structural reorganization: advanced techniques including sharing of operators, and retiming of circuits (moving FFs), and others?2Spring 2005 EECS150 - Lec06-synthesisPage 5Operators• Logical operators map into primitive logic gates• Arithmetic operators map into adders, subtractors, …– Unsigned 2s complement– Model carry: target is one-bit wider that source– Watch out for *, %, and /• Relational operators generate comparators• Shifts by constant amount are just wire connections– No logic involved• Variable shift amounts a whole different story --- shifter• Conditional expression generates logic or MUXY = ~X << 2X[3]Y[0]Y[1]Y[2]X[0]X[1]X[2]Y[3]Y[4]Y[5]Spring 2005 EECS150 - Lec06-synthesisPage 6Synthesis vs Compilation1561CLevels of RepresentationHigh Level Language Program (e.g., C)Assembly Language Program (e.g.,MIPS)Machine Language Program (MIPS)Control Signal SpecificationCompilerAssemblerMachine Interpretationtemp = v[k];v[k] = v[k+1];v[k+1] = temp;lw $to, 0($2)lw $t1, 4($2)sw$t1, 0($2)sw$t0, 4($2)0000 1001 1100 0110 1010 1111 0101 10001010 1111 0101 1000 0000 1001 1100 0110 1100 0110 1010 1111 0101 1000 0000 1001 0101 1000 0000 1001 1100 0110 1010 1111°°• Compiler – recognizes all possible constructs in a formally defined program language– translates them to a machine language representation of execution process• Synthesis– Recognizes a target dependent subset of a hardware description language– Maps to collection of concrete hardware resources– Iterative tool in the design flowSpring 2005 EECS150 - Lec06-synthesisPage 7Simple Examplemodule foo (a,b,s0,s1,f);input [3:0] a;input [3:0] b;input s0,s1;output [3:0] f;reg f;always @ (a or b or s0 or s1)if (!s0 && s1 || s0) f=a; else f=b;endmodule• Should expand if-else into 4-bit wide multiplexor and optimize the control logic:Spring 2005 EECS150 - Lec06-synthesisPage 8Module Templatemodule <top_module_name>(<port list>);/* Port declarations. followed by wire, reg, integer, task and function declarations *//* Describe hardware with one or more continuous assignments, always blocks, module instantiations and gate instantiations */// Continuous assignmentwire <result_signal_name>;assign <result_signal_name> = <expression>;// always blockalways @(<event expression>)begin// Procedural assignments// if statements// case, casex, and casez statements// while, repeat and for loops// user task and user function callsend// Module instantiation<module_name> <instance_name> (<port list>);// Instantiation of built-in gate primitivegate_type_keyword (<port list>);endmodule• The order of these statements is irrelevant, all execute concurrently.• The statements between the beginand end in an always block execute sequentially from top to bottom. (However, beware of blocking versus non-blocking assignment)• Statements within a fork-join statement in an always block execute concurrently.Synthesis tools expects to find modules in this format.3Spring 2005 EECS150 - Lec06-synthesisPage 9Procedural Assignments• Verilog has two types of assignments within always blocks:• Blocking procedural assignment “=“– The RHS is executed and the assignment is completed before the next statement is executed. Example:Assume A holds the value 1 … A=2; B=A; A is left with 2, B with 2.• Non-blocking procedural assignment “<=“– The RHS is executed and assignment takes place at the end of the current time step (not clock cycle). Example:Assume A holds the value 1 … A<=2; B<=A; A is left with 2, B with 1.• The notion of the “current time step” is tricky in synthesis, so to guarantee that your simulation matches the behavior of the synthesized circuit, follow these rules:i. Use blocking assignments to model combinational logic within an always block.ii. Use non-blocking assignments to implement sequential logic.iii. Do not mix blocking and non-blocking assignments in the same always block.iv. Do not make assignments to the same variable from more than one always block.Spring 2005 EECS150 - Lec06-synthesisPage 10Supported Verilog Constructs– Net types: wire, tri, supply1, supply0; register types: reg, integer, time (64 bit reg); arrays of reg.– Continuous assignments.– Gate primitive and module instantiations.– always blocks, user tasks, user functions.– inputs, outputs, and inouts to a module.– All operators (+, -, *, /, %, <, >, <=, >=, ==, !=, ===, !==, &&, ||, !, ~, &, ~&, |, ~|, ^~, ~^, ^, <<, >>, ?:, { }, {{ }}) [Note: / and % are supported for compile-time constants and
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