CS 150 – Spring 2007 - Lec #25 – Design Methodology – 1Digital Design Methodology (Revisited)! Design Methodology" Design Specification" Verification" Synthesis! Technology Options" Full Custom VLSI" Standard Cell ASIC" FPGACS 150 – Spring 2007 - Lec #25 – Design Methodology – 2Design Methodology: Big PictureDesign SpecificationDesign PartitionDesign EntryBehavioral ModelingSimulation/FunctionalVerificationPre-SynthesisSign-OffSynthesize and MapGate-level Net ListPostsynthesisDesign ValidationPostsynthesisTiming VerificationTest Generation andFault SimulationCell Placement/ScanInsertation/RoutingVerify Physical andElectrical RulesSynthesize and MapGate-level Net ListDesign IntegrationAnd VerificationDesign Sign-OffCS 150 – Spring 2007 - Lec #25 – Design Methodology – 3Design Specification! Written statement of functionality, timing, area,power, testability, fault coverage, etc.! Functional specification methods:" State Transition Graphs" Timing Charts" Algorithm State Machines (like flowcharts)" HDLs (Verilog and VHDL)CS 150 – Spring 2007 - Lec #25 – Design Methodology – 4Design Partition! Partition to form an Architecture" Interacting functional units# Control vs. datapath separation# Interconnection structures within datapath# Structural design descriptions" Components described by their behaviorals# Register-transfer descriptions" Top-down design method exploiting hierarchy and reuse ofdesign effortCS 150 – Spring 2007 - Lec #25 – Design Methodology – 5Design Entry! Primary modern method: hardware description language" Higher productivity than schematic entry" Inherently easy to document" Easier to debug and correct" Easy to change/extend and hence experiment with alternativearchitectures! Synthesis tools map description into generic technologydescription" E.g., logic equations or gates that will subsequently be mapped intodetailed target technology" Allows this stage to be technology independent (e.g., FPGA LUTs orASIC standard cell libraries)! Behavioral descriptions are how it is done in industry todayCS 150 – Spring 2007 - Lec #25 – Design Methodology – 6Simulation and Functional Verification! Simulation vs. Formal Methods! Test Plan Development" What functions are to be tested and how" Testbench Development# Testing of independent modules# Testing of composed modules" Test Execution and Model Verification# Errors in design# Errors in description syntax# Ensure that the design can be synthesized" The model must be VERIFIED before the design methodology canproceedCS 150 – Spring 2007 - Lec #25 – Design Methodology – 7Design Integration and Verification! Integrate and test the individual components thathave been independently verified! Appropriate testbench development and integration! Extremely important step and one that is often thesource of the biggest problems" Individual modules thoroughly tested" Integration not as carefully tested" Bugs lurking in the interface behavior among modules!CS 150 – Spring 2007 - Lec #25 – Design Methodology – 8Presynthesis Sign-off! Demonstrate full functionality of the design! Make sure that the behavior specification meets thedesign specification" Does the demonstrated input/output behavior of the HDLdescription represent that which is expected from theoriginal design specification! Sign-off only when all functional errors have beeneliminatedCS 150 – Spring 2007 - Lec #25 – Design Methodology – 9Gate-Level Synthesis and TechnologyMapping! Once all syntax and functional errors have been eliminated,synthesize the design from the behavior description" Optimized Boolean description" Map onto target technology! Optimizations include" Minimize logic" Reduce area" Reduce power" Balance speed vs. other resources consumed! Produces netlist of standard cells or database to configuretarget FPGACS 150 – Spring 2007 - Lec #25 – Design Methodology – 10Postsynthesis Design Validation! Does gate-level synthesized logic implement the sameinput-output function as the HDL behavioraldescription?VerilogBehavioral DescGate-Level DescLogicSynthesisStimulusGeneratorTestbench for PostsynthesisDesign ValidationResponseComparatorCS 150 – Spring 2007 - Lec #25 – Design Methodology – 11Postsynthesis Timing Verification! Are the timing specifications met?! Are the speeds adequate on the critical paths?" Can’t accurately be determined until actual physical layout isunderstood and analyzed—length of wires, relative placementof sources and sinks, number of switch matrix crosspointstraversed, etc.! Resynthesis may be required to achieve timing goals" Resize transistors" Modify architecture" Choose a different target device or technologyCS 150 – Spring 2007 - Lec #25 – Design Methodology – 12Test Generation and Fault Simulation! This is NOT about debugging the design!" Design should be correct at this stage, so …! Determine set of test vectors to test for inherent fabricationflaws" Need a quick method to sort out the bad from the good chips" More exhaustive testing may be necessary for chips that pass thefirst level" More relevant for ASIC design than FPGAs# Avoiding this step is one of the advantages of using the FPGA approach! Fault simulation is used to determine how complete are the testvectorsCS 150 – Spring 2007 - Lec #25 – Design Methodology – 13Placement and Routing! ASIC Standard Cells" Select the cells and placement them on the mask" Interconnect the placed cells" Choose implementation scheme for critical signals# E.g., Clock distribution trees to minimize skew" Insert scan paths! FPGAs" Placing functions into particular CLBs/Slices and committinginterconnections to particular wires in the switch matrixCS 150 – Spring 2007 - Lec #25 – Design Methodology – 14Physical and Electrical Design Rule Check! Applies to ASICs primarily" Are mask geometries correct to insure high probability ofsuccessful fabrication?" Fan-outs correct? Crosstalk signals within specification?Current drops within specification? Noise levels ok? Powerdissipation acceptable?! Many of these issues are not significant at a chip levelfor an FPGA but may be an issue for the system thatincorporates the FPGACS 150 – Spring 2007 - Lec #25 – Design Methodology – 15Parasitic Extraction! Extract geometric information from design todetermine capacitance! Yields a much more realistic model of signalperformance and delay! Are the speed (timing) and power goals of the designstill
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