Structural VerilogUCB EECS150 Spring 2010Lab Lecture #2Agenda• CAD Flow Extension• Verilog• Structural Verilog• Administrative Info• Lab #2: A Structural Accumulator– Circuit– Testing– Analysis of resource usage and timing– PreLab• Questions?2UCB EECS150 Spring 2010, Lab Lecture #2CAD Flow Extension (1)3UCB EECS150 Spring 2010, Lab Lecture #2010110001001001101000101010100100101Translate/Map/PARFPGA EditorBitGen iMPACT.ncd.ncd.ncd (optionally modified).bitDesign PartitioningDesign EntryVerilog HDLPrevious Lab (FPGA Editor)Optional stepPPRCAD Flow Extension (2)4UCB EECS150 Spring 2010, Lab Lecture #2010110001001001101000101010100100101Translate/Map/PARFPGA EditorBitGeniMPACT.ncd.ncd.ncd (optionally modified).bitDesign PartitioningDesign EntryBehavioral Verilog HDLSynthesis ToolOptional stepLogic SynthesisSynthesis ToolSimulationModelSimDesign EntryStructural Verilog HDLLab1Lab2Lab3Lab4Lab5DebuggingChipScopeDesign On-boardOff-chip Devices(and beyond)• The Big PictureVerilog (1)• What’s an HDL?– Textual Description of a Circuit– Human and Machine Readable– Hierarchical– Meaningful Naming• NOT A PROGRAM– Describe what the circuit IS– Not what it DOES5UCB EECS150 Spring 2010, Lab Lecture #2Verilog + CAD6UCB EECS150 Spring 2010, Lab Lecture #2design on napkinassign Out = Q ^ In; always @ (posedge Clock) begin if (Reset) Q <= 1’b0; else Q <= In; end notepadCAD ToolsQQSETCLRDInClockOutResetplaced & routed designtextual hardware descriptionVerilog + CAD7UCB EECS150 Spring 2010, Lab Lecture #2design on napkinDesign Entry: express the design in a hardware description language (HDL)hardware descriptionLogic Synthesis: transform behavioral description into a gate-level descriptionGate-level (structural) descriptionDesign Partitioning: transform primitive gates and flip-flops into LUTs and other primitive FPGA elementsNetlistMap: maps the primitive elements in the netlist into components on a specific FPGATranslate: reduce to logic elements expressed in terms that Xilinx-specific devices can understandXilinx database fileNative Circuit Description (not placed, not routed)Native Circuit Description (not routed)Place: determines exactly where, physically, on the FPGA each LUT, flip-flop, and logic gate should be placedNative Circuit Description (complete!)Route: for each signal, choose the path to get that signal from its source to its destinationDigital Design Productivity, Gates/Week • Behavioral HDL 2K-10K• RTL HDL 1K-2K• Gates 100-200• Transistors 10-208UCB EECS150 Spring 2010, Lab Lecture #2Source: DataQuestStructural Verilog (1)• Verilog Subsets – Structural: primitive gates + modules • Gate level design • You will ONLY use Structural Verilog in this lab – Dataflow: compact boolean expressions • More compact expression of structural Verilog– Behavioral: abstract syntax • Timing nuances • You will see this starting next lab 9UCB EECS150 Spring 2010, Lab Lecture #2Structural Verilog (2)• Structural 2:1 Mux example10UCB EECS150 Spring 2010, Lab Lecture #2module Mux21(A, B, S, Out); input wire A, B, S; output wire Out; wire notS, ATemp, BTemp; not invertS(notS, S); and and(ATemp, A, notS), andB(BTemp, B, S); or result(Out, ATemp, BTemp); endmoduleKeyModule wrapperInput/Output wire declarationsWire declarationsGates1 0SABOutABOutSAdministrative Info (1)• Homework submission• Lab lecture conflicts• Card key access• Check-off procedure• Questions?11UCB EECS150 Spring 2010, Lab Lecture #2Lab #2 (1)• Build a structural Accumulator– Work with a real design– Write parameterized Verilog• Debugging– Synplicity RTL/Technology schematic• Analysis– Resource consumption– TimingUCB EECS150 Spring 2010, Lab Lecture #2 12Lab #2 (2)• Structural Accumulator– ALU– ‘FDRSE’ Xilinx primitive flip-flop13UCB EECS150 Spring 2010, Lab Lecture #2ALUInALUOpClockResultLab #2 (3)• ALU – We provide the Verilogfor N-bit version – You must implement the 1-bit ALU model– Must support our ALUOp– Supports: +, -, &, |, ~, pass-through (7 operations)UCB EECS150 Spring 2010, Lab Lecture #2 14ALUBitSliceABALUOp3bResultALUBitSliceALUBitSlice‘generate’ blockCarryOutCarryInCarryOutCarryInCarryOutA[0]B[0]A[1]B[1]A[2]B[2]CarryInALUOp[0]Lab #2 (4)• FDRSE – Xilinx primitive – D-type flip-flop • Instantiated like a simple module • Specific Set/Reset characteristics – “Read all about it!” virtex5_hdl.pdf • It’s part of the PreLab!UCB EECS150 Spring 2010, Lab Lecture #2 15Lab #2 (5)• Accumulator – We give you port specification – You will implement the rest of the circuit • Use code examples – Mux21: Structural Verilog (gates, wires) – ALU: generate statements • Abide by our interfaces!UCB EECS150 Spring 2010, Lab Lecture #2 16Lab #2 (6)• HW test harness – TA Accumulator vs. your Accumulator – Check all input combinations – Signal errorUCB EECS150 Spring 2010, Lab Lecture #2 17Circuit under Test (‘CUT’)ALUOp3bTA CircuitCounterClock==Enable counter?ErrorA ASuccessLab #2 (7)• Circuit Analysis – Resource Usage • Accumulator(width) = how many LUTs / SLICEs? • generate allows you to experiment – Timing • Locate nets “Technology Schematic” • Calculate delay on the nets FPGA Editor UCB EECS150 Spring 2010, Lab Lecture #2 18Lab #2 (8)• PreLab– Read specified material• Virtex-5 Libraries Guide for HDL Designs (FDRSE section)– Design your ALUBitSlice and Accumulator– Write all of your Verilog• Lab starts at debugging phase – Assumption:you have written all of your Verilog ahead of timeUCB EECS150 Spring 2010, Lab Lecture #2 19Acknowledgements & ContributorsSlides developed by Brandon Myers & John Wawrzynek (1/2010).This work is based closely on slides by:Chris Fletcher (2008-2009)Greg Gibeling (2003-2005)This work has been used by the following courses:– UC Berkeley CS150 (Spring 2010): Components and Design Techniques for Digital Systems 20UCB EECS150 Spring 2010, Lab Lecture
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