A quick guide to things that may not be entirely apparent. (Note: this is not a replacementfor the writeup, nor does having read this mean you have sufficient knowledge tocomplete the checkpoint. I just happen to think this is useful data)• Step one: remember what the goals of the checkpoint are:Receive packets and display the summation of the 64 bit segments of their RTPpayloads on the LEDSPossible hazards to this occurring that must be overcome:A garbled packet comes in Solution: CRC check fails, ignore dataA packet from a stream you aren’t Solution: SSRC field is not as expected,displaying comes in ignore dataA packet of some other ether type Solution: MAC type is not as specified(an ARP for instance) arrives ignore dataAn RTP packet comes in with a Solution: RTP payload type is not aspayload type other than the one specified, ignore datafor checkpoint 1• The input to the CRC module has its bits flipped relative to the order they arecoming in. (RX_D 3 -> CRC IN 0, 2 -> 1, etc)• The ordering of the 2 nibbles within a byte is reversed. This issue is taken care ofby a reordering done in the shift register. However, this means that the values inthe shift register are only meaningful on byte aligned boundaries. On non-bytealigned nibble counts, the value of the first byte in the shift register will not bevalid. This should not affect operation of the circuit at higher level, as major statetransitions are byte aligned, but must be noted, as an error in the control of theshift register re-ordering would cause many problems.• The CRC check module should be fed all nibbles of the packet except for those inthe preamble or in the SFD. If the CRC check is successful, the signal CRCErrorwill go low.• For quick reference:Ethernet MAC type for eTV: 0x0107Total RTP header length: 12 bytes = 24 nibblesCheckpoint 1 RTP payload type: 0x2ARTP payload length: 512 bytes = 1024 nibbles• First things to think about when approaching the design of checkpoint 1:Draw out a block diagram of the circuit you hope to produce. Until you have anidea of what it is you want to create there is no point in attempting to use verilogto describe it. You will likely find it useful to make it clear which parts of yourdesign manipulate data and which control the pieces that manipulate data andgroup them
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